154 publications from this institution
Multiplication is a widely used arithmetic operation in microprocessing and digital signal processing applications, and multiplication is realized using a multiplier. This article presents the quasi-delay-insensitive (QDI) early output versions of recently reported indicating asynchronous array multipliers. Delay-insensitive dual-rail encoding is used for data representation and processing, and 4-phase return-to-zero (RTZ) and return-to-one (RTO) handshake protocols are used for data communication. Many QDI array multipliers were realized using a 32/28 nm complementary metal oxide semiconductor (CMOS) technology. Compared to the optimum indicating array multiplier, the proposed optimum early output array multiplier achieves a 6.2% reduction in cycle time and a 7.4% reduction in power-cycle time product (PCTP) with respect to RTZ handshaking, and a 7.6% reduction in cycle time and an 8.8% reduction in PCTP with respect to RTO handshaking without an increase in the area. The simulation results also convey that the RTO handshaking is preferable to the RTZ handshaking for the optimum implementation of QDI array multipliers.
Asynchronous quasi-delay-insensitive (QDI) implementation of approximate addition is described in this article. The objective is to provide an insight into the optimization in design metrics that can be achieved with approximate addition compared to accurate addition based on a QDI implementation by considering a practical digital image processing application. For the QDI implementation, some approximate adder architectures are considered which are deemed suitable for both ASIC and FPGA based implementations. The accurate and approximate adders considered are of size 32-bits. The delay-insensitive dual-rail code was used for data encoding, and four-phase return-to-zero (RTZ) and return-to-one (RTO) handshake protocols were used separately for data communication. The implementations used a 32/28-nm complementary metal oxide semiconductor (CMOS) technology. The simulation results show that an approximate adder HOERAA achieves a 19.7% reduction in cycle time, a 12.5% reduction in area, and an 17.7% reduction in energy compared to the accurate adder for RTZ handshaking. For RTO handshaking, HOERAA achieves an 18.7% reduction in cycle time, a 12.4% reduction in area, and a 16.6% reduction in energy compared to the accurate adder. Another approximate adder HEAA achieves a 19.7% reduction in cycle time, a 12.9% reduction in area, and a 20.2% reduction in energy, compared to the accurate adder for RTZ handshaking. For RTO handshaking, HEAA achieves an 18.7% reduction in cycle time, a 12.9% reduction in area, and a 19.2% reduction in energy compared to the accurate adder. Nevertheless, the RTO handshaking is preferable to RTZ handshaking as the former facilitates slightly better optimizations in design metrics compared to the latter. The mean absolute error (MAE) and the root mean square error (RMSE), which are popular error metrics used in approximate computing, were calculated for the approximate adders and are given for a comparison. While the MAE of HOERAA and HEAA are comparable, HOERAA has 8.6% reduced RMSE compared to HEAA. Digital image processing results based on accurate and approximate additions are also given, to substantiate the usefulness of approximate addition.
