Publications

Space and defence electronics system demands higher reliability for its operation in harsh (Maurer et al. in John Hopkins APL Tech Dig 28, 2008 [1]) and tough application environments. Development of processor (Azambuja et al. in IEEE Trans Nucl Sci 59, 2012 [2])...

New factorized carry lookahead adders corresponding to the regular carry lookahead adder (RCLA) architecture viz. the factorized regular carry lookahead adder (FRCLA), and the block carry lookahead adder (BCLA) architecture viz. the factorized block carry lookahead adder (FBCLA) are presented. The idea behind the proposed factorized carry lookahead adders is discussed and example implementations are provided. The RCLA, BCLA, FRCLA and FBCLA were realized using the gates of a 32/28nm CMOS standard digital cell library. The results show that the proposed FRCLA achieves an average reduction in the power-delay product i.e., energy by 7.85% for 32- and 64-bit additions compared to the best among the rest.

This Informational RFC describes Data Center TCP (DCTCP): a TCP congestion control scheme for data-center traffic. DCTCP extends the Explicit Congestion Notification (ECN) processing to estimate the fraction of bytes that encounter congestion rather than simply detecting that some congestion has occurred. DCTCP then scales the TCP congestion window based on this estimate. This method achieves high- burst tolerance, low latency, and high throughput with shallow- buffered switches. This memo also discusses deployment issues related to the coexistence of DCTCP and conventional TCP, discusses the lack of a negotiating mechanism between sender and receiver, and presents some possible mitigations. This memo documents DCTCP as currently implemented by several major operating systems. DCTCP, as described in this specification, is applicable to deployments in controlled environments like data centers, but it must not be deployed over the public Internet without additional measures.

We present a new asynchronous quasi-delay-insensitive (QDI) block carry lookahead adder with redundancy carry (BCLARC) realized using delay-insensitive dual-rail data encoding and 4-phase return-to-zero (RTZ) and 4-phase return-to-one (RTO) handshaking. The proposed QDI BCLARC is found to be faster and energy-efficient than the existing asynchronous adders which are QDI and non-QDI (i.e., relative-timed). Compared to existing asynchronous adders corresponding to various architectures such as ripple carry adder (RCA), conventional carry lookahead adder (CCLA), carry select adder (CSLA), BCLARC, and hybrid BCLARC-RCA, the proposed BCLARC is found to be faster and more energy-optimised. The cycle time (CT), which is the sum of forward and reverse latencies, governs the speed; and the product of average power dissipation and cycle time viz. the power-cycle time product (PCTP) defines the low power/energy efficiency. For a 32-bit addition, the proposed QDI BCLARC achieves the following average reductions in design metrics over its counterparts when considering RTZ and RTO handshaking: i) 20.5% and 19.6% reductions in CT and PCTP respectively compared to an optimum QDI early output RCA, ii) 16.5% and 15.8% reductions in CT and PCTP respectively compared to an optimum relative-timed RCA, iii) 32.9% and 35.9% reductions in CT and PCTP respectively compared to an optimum uniform input-partitioned QDI early output CSLA, iv) 47.5% and 47.2% reductions in CT and PCTP respectively compared to an optimum QDI early output CCLA, v) 14.2% and 27.3% reductions in CT and PCTP respectively compared to an optimum QDI early output BCLARC, and vi) 12.2% and 11.6% reductions in CT and PCTP respectively compared to an optimum QDI early output hybrid BCLARC-RCA. The adders were implemented using a 32/28nm CMOS technology.

Monotonic circuits are a class of input–output mode (IOM) asynchronous circuits that are relaxed compared to quasi-delay-insensitive (QDI) IOM asynchronous circuits in terms of signaling the completion of internal processing. Some recent works have demonstrated the superiority of monotonic logic over QDI logic for arithmetic circuits such as adders and multipliers. This paper presents a new monotonic asynchronous two-bit full adder (TFA) that can be duplicated and cascaded to form a ripple-carry adder (RCA). While an RCA is a slow adder with respect to synchronous design, with respect to IOM asynchronous design an RCA is a noteworthy adder since it has perhaps the least reverse latency that is not attainable through other IOM asynchronous adders. Conventionally, an RCA is constructed via a cascade of one-bit full adders (OFAs). An OFA adds two input bits along with any carry input and produces a sum bit and any carry output. On the other hand, a TFA simultaneously adds two pairs of input bits along with any carry input and produces two sum bits and any carry output. Using our proposed monotonic TFA, we realized an RCA to compare its performance with RCAs constructed using different asynchronous OFAs, and RCAs constructed using existing TFAs. We considered the popular delay-insensitive dual-rail scheme for encoding the adder inputs and outputs, and two 4-phase handshake protocols, namely return-to-zero handshaking (R0H) and return-to-one handshaking (R1H) for communication separately. We used a 28 nm CMOS process for implementation and considered a 32-bit addition as an example. Based on the design metrics estimated, the following inferences were derived: (i) compared to the RCA using the state-of-the-art monotonic OFA, the RCA incorporating the proposed TFA achieved a 26% reduction in cycle time for R0H and a 28.5% reduction in cycle time for R1H while dissipating almost the same power; the cycle time governs the data application rate in an IOM asynchronous circuit, and (ii) compared to the RCA comprising an early output QDI TFA, the RCA incorporating the proposed TFA achieved a 22.3% reduction in cycle time for R0H and a 25.4% reduction in cycle time for R1H while dissipating moderately less power. Also, compared to the existing early output QDI TFA, the proposed TFA occupies 40.9% less area for R0H and 42% less area for R1H.

Addition is a fundamental computer arithmetic operation that is widely performed in microprocessors, digital signal processors, and application-specific processors. The design of a high-speed and energy-efficient adder is thus useful and important for practical applications. In this context, this paper presents the designs of novel asynchronous carry look-ahead adders (CLAs) viz. a standard CLA (SCLA) and a block CLA (BCLA). The proposed CLAs are monotonic, dual-rail encoded, and are realized according to return-to-zero handshake (RZH) and return-to-one handshake (ROH) protocols using a 28-nm CMOS process technology. The proposed BCLA has a slight edge over the proposed SCLA, and the proposed BCLA reports the following optimizations in design metrics such as cycle time (delay), area, and power compared to a recently presented state-of-the-art asynchronous CLA for a 32-bit addition: (i) 32.6% reduction in cycle time, 29% reduction in area, 4.3% reduction in power, and 35.5% reduction in energy for RZH, and (ii) 31.4% reduction in cycle time, 28.9% reduction in area, 4.4% reduction in power, and 34.4% reduction in energy for ROH. Also, the proposed BCLA reports reductions in cycle time and power/energy compared to many other asynchronous adders.

No abstract is provided for this article.

This article presents a new asynchronous early output 3-input majority voter that is used to realize a high-speed, low power and less area occupying relative-timed asynchronous TMR implementation. The proposed majority voter is used to realize an asynchronous TMR implementation and it is compared with asynchronous TMR implementations realized using other asynchronous majority voters. The dual-rail code was used for data encoding and two kinds of four-phase handshaking were used for data communication. Compared to the existing implementations, we find that the proposed asynchronous majority voter leads to an efficient TMR implementation by simultaneously reducing the cycle time, silicon area, and average power dissipation by 25.1%, 7.5% and 7.8% respectively, on average. The implementations used a 32/28 nm CMOS process technology.

In the domain of combinational logic synthesis, simplification of functions based on AND-OR logic is a well studied area. However, since many real-life combinational functions are XOR dominated, efficient AND-XOR decomposition can lead to more compact realization of such circuits [1], Amongst the AND-XOR logic expressions, although there are several classes [1] viz. RM, PPRM, FPRM, KRO, PSDKRO, GRM and ESOP, ESOPs are the most general Reed-Muller forms with interesting properties. Practically speaking, they have numerous applications in synthesis and design-for-test [3]. This work extends the originally proposed method of [1] [4], addressing the problem of ESOP minimization, by adding simple algebraic factorization operations. Besides, with new binary matrices of order '2 times n', we illustrate how to simplify even irreducible ESOP forms. We make it clear that XOR (XNOR) intensive combinational logic could effectively be implemented using five types of logic gates, namely XOR XNOR, NAND, NOR and NOT, in comparison with some of the solutions obtained in [10] [11]. The proposed synthesis solution is quantitatively evaluated on the basis of power consumption metric, after technology-mapping based on static CMOS logic style, with a 0.35 micron TSMC process technology.

The aim of this paper is to analyze the impact of local and global indication on a self-timed system architecture. Towards this end, we investigate the effect of these two indicating frameworks with respect to a 32-bit self-timed carry-ripple adder, constructed using a cascade of self-timed dual-bit adder modules. In both cases, the self-timed ripple carry adder corresponds to weak-indication. We consider the analysis from the perspective of both homogeneous and heterogeneous encoding of data, employing unordered delay-insensitive codes. The simulation results reveal that global indication benefits in terms of minimizing the power and area parameters while reporting a performance advantage over local indication.

Authors make a change because the modification is required to ensure the accuracy of a result [...]

This paper presents a novel Fault-tolerant design i.e., redundancy strategy based on Approximate Computing, which we call FAC. Conventionally, triple modular redundancy (TMR) has been widely used to guarantee 100% tolerance to any single fault or failure of a processing unit where the processing unit may be a circuit or system. However, TMR results in more than 200% overhead in area and power compared to a single processing unit. To reduce the overheads in design metrics associated with TMR, alternative redundancy approaches were presented in the literature but they guarantee only partial or moderate fault tolerance. Nevertheless, among these alternative redundancy approaches, the majority voter-based reduced precision redundancy (MVRPR) may be useful for naturally error-resilient applications like digital signal processing which is commonly used in space systems. The proposed FAC is ideally suited for error-resilient applications but unlike MVRPR which guarantees only a moderate fault tolerance, FAC guarantees a 100% tolerance to any single fault or failure of a processing unit like TMR. We considered TMR, MVRPR, and FAC to comparatively evaluate their performance for a digital image processing application. The image processing results obtained demonstrate the usefulness of FAC. Further, for a physical implementation using a 28-nm CMOS technology, FAC achieves a 15.3% reduction in delay, 19.5% reduction in area, and a 24.7% reduction in power compared to TMR, and an 18% reduction in delay, 5.4% reduction in area, and 11.2% reduction in power compared to MVRPR.

This paper discusses the standard cell based designs of asynchronous carry select adders (CSLAs) corresponding to strong-indication, weak-indication, and early output timing regimes realized using a delay-insensitive dual-rail code for data representation and processing, and a 4-phase return-to-zero protocol for handshaking. Many 32-bit asynchronous CSLAs corresponding to a uniform input partition viz. 8-8-8-8 and a non-uniform input partition viz. 8-7-6-4-3-2-2 were considered for implementation and comparison. All the asynchronous CSLAs were physically realized in semi-custom ASIC design style using a 32/28 nm CMOS process technology. The simulation results show that the 32-bit early output asynchronous CSLA based on the uniform input partition (8-8-8-8) enables optimized data path latency, area occupancy, and average power dissipation compared to the rest.

It is common knowledge that carry look-ahead adders constitute a high-speed method of performing binary addition in logarithmic time. As an improvement, in this paper, FPGA based realization of high-speed carry look-ahead adders based on the concept of section-carry is discussed. Three kinds of carry look-ahead adder architectures viz. Type 1, Type 2, Mixed are presented. In comparison with conventional carry look-ahead adders of sizes 16, 32 and 64-bits, the proposed section-carry based carry look-ahead adders report improvements in speed of 14.9%, 12.1% and 13% for Type 1, Type 2 and Mixed topologies respectively, for simulations targeting a 90nm FPGA device.

In this study the free vibration of circumferentially periodic structures has been analysed using the block Lanczos method in a semi complex domain for extracting real natural frequencies and complex mode shapes. The influence of the number of vectors in the block and also the effect of renumbering of nodes, depending on whether they are internal, adjacent or boundary nodes, on the CPU time are studied. The efficiency of the present method is compared with the subspace iteration schemes.

In this paper, conventional gate-level circuit compositions of the totally self-checking two-rail checker unit and the 2-of-4 checker unit are revisited. With respect to the former (latter), when the two input code words compared is not complementary (if two 1's are not present in the four input rails) and in the presence of an internal stuck-at fault, the checker is no more fault secure. In both the cases, the checker ceases to be totally self-checking. Given this, we suggest suitable cell based designs to overcome the above drawbacks. Hence, this work presents a new insight into combinational checker circuits.

This research correspondence comments on “Asynchronous Logic Implementation Based on Factorized DIMS” [Journal of Circuits, Systems, and Computers, vol. 26, no. 5, pp. 1750087-1-1750087-9, May 2017] with respect to two problematic issues: i) the gate orphan problem implicit in the factorized DIMS approach discussed in the referenced article which affects its strong-indication, and ii) how the enumeration of product terms to represent the synthesis cost is skewed in the referenced article because the logic expression contains sum of products and also product of sums. It is observed that the referenced article has not provided a general logic synthesis algorithm excepting only an example illustration involving a 3-input AND logic function. The absence of a general logic synthesis algorithm would make it difficult to reproduce the research described in the referenced article. Moreover, the example illustration in the referenced article describes an unsafe quasi-delay-insensitive logic decomposition which is not suitable for the multi-level synthesis of strong-indication asynchronous circuits. Further, a logic synthesis method which safely decomposes the DIMS solution to synthesize multi-level strong-indication asynchronous circuits is available in the existing literature, which was neither cited nor taken up for comparison in the referenced article, which is another drawback. Subsequently, it is concluded that the referenced article has not advanced existing knowledge in the field but on the contrary, has caused confusions. Hence, in the interest of readers, this work additionally highlights some important and relevant literature which provide valuable information about robust asynchronous circuit synthesis techniques which employ delay-insensitive codes for data representation and processing and a 4-phase handshake protocol (return-to-zero) for data communication.

Addition is a fundamental operation in microprocessing and digital signal processing hardware, which is physically realized using an adder. The carry-lookahead adder (CLA) and the carry-select adder (CSLA) are two popular high-speed, low-power adder architectures. The speed performance of a CLA architecture can be improved by adopting a hybrid CLA architecture which employs a small-size ripple-carry adder (RCA) to replace a sub-CLA in the least significant bit positions. On the other hand, the power dissipation of a CSLA employing full adders and 2:1 multiplexers can be reduced by utilizing binary-to-excess-1 code (BEC) converters. In the literature, the designs of many CLAs and CSLAs were described separately. It would be useful to have a direct comparison of their performances based on the design metrics. Hence, we implemented homogeneous and hybrid CLAs, and CSLAs with and without the BEC converters by considering 32-bit accurate and approximate additions to facilitate a comparison. For the gate-level implementations, we considered a 32/28 nm complementary metal-oxide-semiconductor (CMOS) process targeting a typical-case process–voltage–temperature (PVT) specification. The results show that the hybrid CLA/RCA architecture is preferable among the CLA and CSLA architectures from the speed and power perspectives to perform accurate and approximate additions.

We introduce a new carry look-ahead adder (NCLA) architecture that employs non-uniform-size carry look-ahead adder (CLA) modules, in contrast to the conventional CLA (CCLA) architecture, which utilizes uniform-size CLA modules. We adopted two strategies for the implementation of the NCLA. Our novel approach enables improved speed and energy efficiency for the NCLA architecture compared to the CCLA architecture without incurring significant area and power penalties. Various adders were implemented to demonstrate the advantages of NCLA, ranging from the slower ripple carry adder to the widely regarded fastest parallel-prefix adder viz. the Kogge–Stone adder, and their performance metrics were compared. The 32-bit addition was used as an example, with the adders implemented using a semi-custom design method and a 28 nm CMOS standard cell library. Synthesis results show that the NCLA architecture offers substantial improvements in design metrics compared to its high-speed counterparts. Specifically, an NCLA achieved (i) a 14.7% reduction in delay and a 13.4% reduction in energy compared to an optimized CCLA, while occupying slightly more area; (ii) a 42.1% reduction in delay and a 58.3% reduction in energy compared to a conditional sum adder, with an 8% increase in the area; (iii) a 14.7% reduction in delay and a 37.7% reduction in energy compared to an optimized carry select adder, while requiring 37% less area; and (iv) a 20.2% reduction in energy and a 55.4% reduction in area compared to the Kogge–Stone adder.