154 publications from this institution
Cell based self-timed synthesis of recursive carry lookahead adders (RCLA) utilizing generate, propagate and kill functions is described in this paper, and are compared with the recently proposed designs of self-timed section-carry based carry lookahead (SCBCLA) adders. From the simulation results corresponding to a 130nm CMOS process, it is found that with 2-bit CLA, the RCLA adder dissipates 20.2% less power than the SCBCLA adder. With 4-bit CLA, the RCLA adder reports power reduction by 16.5% than the SCBCLA adder. Further, for addition widths ranging from 32 to 64-bits, RCLA adders consume 19% less average power compared to SCBCLA adders.
No abstract is provided for this article.
In the era of nanoelectronics, multiple faults or failures of function blocks are likely to occur. To withstand these, higher levels of redundancy are suggested to be employed in at least the sensitive portions of a circuit or system. In this context, the N-modular redundancy (NMR) scheme may be used to guard against the multiple faults or failures of function blocks. However, the NMR scheme would exacerbate the weight, cost, and design metrics to implement higher-order redundancy. Hence, as an alternative to the NMR, the majority and minority voted redundancy (MMR) scheme was proposed recently. However, the proposal was restricted to the basic implementation with no provision for indicating the correct or the incorrect operation of the MMR. Hence in this work, we present the MMR scheme with the error/no-error signaling logic (ESL). Example NMR circuits without and with the ESL (NMRESL), and example MMR circuits without and with the proposed ESL (MMRESL) were implemented to achieve similar degrees of fault tolerance using a 32/28-nm CMOS technology. The results show that, on average, the proposed MMRESL circuits have 18.9% less critical path delay, dissipate 64.8% less power, and require 49.5% less silicon area compared to their counterpart NMRESL circuits.
No abstract is provided for this article.
The distributed minority and majority voting-based redundancy (DMMR) scheme was proposed as an efficient alternative to the conventional N-modular redundancy (NMR) scheme for the design of mission and safety-critical circuits and systems. However, only a basic implementation of the DMMR scheme was considered with no provision for indicating any fault or error in the DMMR system when they might occur. In this context, this paper presents the novel design of a generic system health indicator (SHI) for the DMMR scheme. Compared to the basic DMMR system, the DMMR system with the proposed SHI can provide concurrent information about the state of the system, i.e., whether the system is healthy or not. This helps to improve the observability of the DMMR system which could be useful during the online testing and/or troubleshooting of any faulty zones in the system, pre-emptively or during any scheduled maintenance. Example DMMR systems and their corresponding NMR systems without and with SHI have been implemented using a 32/28nm CMOS process and compared. On average, the DMMR systems with the proposed SHI report 6.5× improvement in a normalized figure of merit compared to the corresponding NMR systems incorporating SHI.
A standard cell based gate level synchronous full adder design is presented in this paper. The main highlight of the article is that the proposed full adder realization is found to be better in terms of power-delay product (PDP), even in comparison with the full adder element that has been made available as part of two commercial standard cell libraries viz. the high-speed 130nm Faraday (UMC) bulk CMOS process technology and the low Vt but inherently power optimized 65nm STMicroelectronics bulk CMOS process. The fundamental ripple carry adder (RCA) topology is considered to demonstrate the power efficiency of our full adder module vis-a-vis many other recently proposed full adder module designs.
This paper presents a novel technique for gate- level design of combinatorial logic as weakly indicating function blocks. The input state space associated with a function block expands exponentially with a gradual increase in the number of inputs. As a result, large area overhead would incur for an asynchronous realization. Hence, a novel design methodology for realizing combinational logic as a function block is developed under the discipline of quasi-delay-insensitivity with four-phase handshaking and dual-rail encoding, whilst trying to mitigate the area overhead. The focus is on design adhering to the weakly indicating timing regime. Based on analysis with some combinational benchmarks and widely used logic circuit functionality, the proposed method is found to enable compact realizations and appears to be promising for weakly indicating function block design comprising many inputs and outputs.
Space and defence electronics system demands higher reliability for its operation in harsh (Maurer et al. in John Hopkins APL Tech Dig 28, 2008 [1]) and tough application environments. Development of processor (Azambuja et al. in IEEE Trans Nucl Sci 59, 2012 [2])...
Monotonic circuits are a class of input–output mode (IOM) asynchronous circuits that are relaxed compared to quasi-delay-insensitive (QDI) IOM asynchronous circuits in terms of signaling the completion of internal processing. Some recent works have demonstrated the superiority of monotonic logic over QDI logic for arithmetic circuits such as adders and multipliers. This paper presents a new monotonic asynchronous two-bit full adder (TFA) that can be duplicated and cascaded to form a ripple-carry adder (RCA). While an RCA is a slow adder with respect to synchronous design, with respect to IOM asynchronous design an RCA is a noteworthy adder since it has perhaps the least reverse latency that is not attainable through other IOM asynchronous adders. Conventionally, an RCA is constructed via a cascade of one-bit full adders (OFAs). An OFA adds two input bits along with any carry input and produces a sum bit and any carry output. On the other hand, a TFA simultaneously adds two pairs of input bits along with any carry input and produces two sum bits and any carry output. Using our proposed monotonic TFA, we realized an RCA to compare its performance with RCAs constructed using different asynchronous OFAs, and RCAs constructed using existing TFAs. We considered the popular delay-insensitive dual-rail scheme for encoding the adder inputs and outputs, and two 4-phase handshake protocols, namely return-to-zero handshaking (R0H) and return-to-one handshaking (R1H) for communication separately. We used a 28 nm CMOS process for implementation and considered a 32-bit addition as an example. Based on the design metrics estimated, the following inferences were derived: (i) compared to the RCA using the state-of-the-art monotonic OFA, the RCA incorporating the proposed TFA achieved a 26% reduction in cycle time for R0H and a 28.5% reduction in cycle time for R1H while dissipating almost the same power; the cycle time governs the data application rate in an IOM asynchronous circuit, and (ii) compared to the RCA comprising an early output QDI TFA, the RCA incorporating the proposed TFA achieved a 22.3% reduction in cycle time for R0H and a 25.4% reduction in cycle time for R1H while dissipating moderately less power. Also, compared to the existing early output QDI TFA, the proposed TFA occupies 40.9% less area for R0H and 42% less area for R1H.
The delay-insensitive minterm synthesis (DIMS) method facilitates a robust two-level asynchronous implementation of dual-rail encoded arbitrary combinational logic. However for multilevel realization, logic decomposition becomes indispensable. In this context, this paper describes an elegant technique of performing quasi-delay-insensitive logic decomposition based on set theoretic principles. This includes consideration of generic homogeneous and heterogeneous delay-insensitive data encoding schemes within the purview of the DIMS approach. Through the proposed set theory based logic decomposition rules, it is shown how any combinational logic specification that comprises any number of concurrent inputs can be synthesized in a multilevel fashion on the basis of the DIMS method without compromising on circuit robustness.
No abstract is provided for this article.
Multiplication is a basic arithmetic operation that is encountered in almost all general-purpose microprocessing and digital signal processing applications, and multiplication is physically realized using a multiplier. This paper discusses the physical implementation of indicating asynchronous multipliers, which are inherently elastic and are robust to timing, process, and parametric variations, and are modular. We consider the physical implementation of many weak-indication asynchronous multipliers using a 32/28-nm CMOS technology by adopting the array multiplier architecture. The multipliers are synthesized in a semi-custom ASIC-design style. The 4-phase return-to-zero (RTZ) and the 4-phase return-to-one (RTO) handshake protocols are considered for the data communication. The multipliers are realized using strong-indication or weak-indication full adders. Strong-indication 2-input AND function is used to generate the partial products in the case of both RTZ and RTO handshaking. The full adders considered are derived from different indicating asynchronous logic design methods. Among the multipliers considered, a weak-indication asynchronous multiplier utilizing the biased weak-indication full adder is found to be efficient in terms of the cycle time and the power-cycle time product with respect to both RTZ and RTO handshaking. Also, the 4-phase RTO handshake protocol is found to be preferable than the 4-phase RTZ handshake protocol for achieving enhanced optimizations in the design metrics.
A new asynchronous early output, relative-timed block carry lookahead adder (BCLA) incorporating redundant carries is proposed. Compared to the best of existing semi-custom asynchronous carry lookahead adders (CLAs) employing delay-insensitive data encoding and following a 4-phase handshaking, the proposed BCLA with redundant carries achieves 14.9% reduction in cycle time and 12.3% reduction in area with no power penalty. A hybrid variant involving a ripple carry adder (RCA) in the least significant stages i.e. BCLA-RCA is also considered that achieves 15.2% reduction in cycle time and 11.2% reduction in area over the best of existing hybrid CLARCA variants without power penalty.
Approximate ripple carry adders (RCAs) and carry lookahead adders (CLAs) are presented which are compared with accurate RCAs and CLAs for performing a 32-bit addition. The accurate and approximate RCAs and CLAs are implemented using a 32/28nm CMOS process. Approximations ranging from 4- to 20-bits are considered for the less significant adder bit positions. The simulation results show that approximate RCAs report reductions in the power-delay product (PDP) ranging from 19.5% to 82% than the accurate RCA for approximation sizes varying from 4- to 20-bits. Also, approximate CLAs report reductions in PDP ranging from 16.7% to 74.2% than the accurate CLA for approximation sizes varying from 4- to 20-bits. On average, for the approximation sizes considered, it is observed that approximate CLAs achieve a 46.5% reduction in PDP compared to the approximate RCAs. Hence, approximate CLAs are preferable over approximate RCAs for the low power implementation of approximate computer arithmetic.
Approximate or inaccurate addition is found to be viable for practical applications which have an inherent error tolerance. Approximate addition is realized using an approximate adder, and many approximate adder designs have been put forward in the literature targeting an acceptable trade-off between quality of results and savings in design metrics compared to the accurate adder. Approximate adders can be classified into three categories as: (a) suitable for FPGA implementation, (b) suitable for ASIC type implementation, and (c) suitable for FPGA and ASIC type implementations. Among these, approximate adders, which are suitable for FPGA and ASIC type implementations are particularly interesting given their versatility and they are typically designed at the gate level. Depending on the way approximation is built into an approximate adder, approximate adders can be classified into two kinds as static approximate adders and dynamic approximate adders. This paper compares and analyzes static approximate adders which are suitable for both FPGA and ASIC type implementations. We consider many static approximate adders and evaluate their performance for a digital image processing application using standard figures of merit such as peak signal to noise ratio and structural similarity index metric. We provide the error metrics of approximate adders, and the design metrics of accurate and approximate adders corresponding to FPGA and ASIC type implementations. For the FPGA implementation, we considered a Xilinx Artix-7 FPGA, and for an ASIC type implementation, we considered a 32/28 nm CMOS standard digital cell library. While the inferences from this work could serve as a useful reference to determine an optimum static approximate adder for a practical application, in particular, we found approximate adders HOAANED, HERLOA and M-HERLOA to be preferable.
We present a novel fast bipartitioned hybrid adder (FBHA) that utilizes carry-select and carry-lookahead logic. The proposed FBHA is an accurate adder with a si
