Publications

The carry look-ahead adder (CLA) is well known among the family of high-speed adders. However, a conventional CLA is not faster than other high-speed adders such as a conditional sum adder (CSA), a carry-select adder (CSLA), and the Kogge–Stone adder (KSA), which is the fastest parallel-prefix adder. Further, in terms of power-delay product (PDP) that characterizes the energy of digital circuits, the conventional CLA is not efficient compared to CSLA and KSA. In this context, this paper presents a high-speed and energy-efficient architecture for the CLA. Many adders ranging from ripple carry to parallel-prefix adders were implemented using a 32-28 nm CMOS standard digital cell library by considering a 32-bit addition. The adders were structurally described in Verilog and synthesized using Synopsys Design Compiler. From the results obtained, it is observed that the proposed CLA achieves a reduction in critical path delay by 55.3% and a reduction in PDP by 45% compared to the conventional CLA. Compared to the CSA, the proposed CLA achieves a reduction in critical path delay by 33.9%, a reduction in power by 26.1%, and a reduction in PDP by 51.1%. Compared to an optimized CSLA, the proposed CLA achieves a reduction in power by 35.4%, a reduction in area by 37.3%, and a reduction in PDP by 37.1% without sacrificing the speed. Although the KSA is faster, the proposed CLA achieves a reduction in power by 39.6%, a reduction in PDP by 6.5%, and a reduction in area by 55.6% in comparison.

This paper presents a new input-output mode asynchronous full adder that is monotonic and early output type. In a monotonic asynchronous circuit, the intermediate outputs and primary outputs experience similar signal transitions as the primary inputs for the application of data and/or spacer. The proposed full adder exhibits monotonicity for processing data and spacer. The full adder employs dual-rail encoding for inputs and outputs and corresponds to return-to-zero handshaking. The early output nature of the proposed full adder could facilitate the production of sum and carry outputs based on the adder inputs without having to wait for the carry input when the spacer is supplied. When incorporated in a ripple carry adder (RCA) structure, the proposed full adder enables reductions in all the design metrics viz. cycle time, area, and total power dissipation compared to existing gate-level asynchronous full adders. Compared to the best of the existing high-speed asynchronous full adders, the proposed full adder enables a 10.4% reduction in cycle time and a 15.8% reduction in area without any power penalty when incorporated in a 32-bit RCA, for implementation using a 28-nm CMOS technology. In terms of power-cycle time product, which is representative of energy, the proposed full adder enables an 11.8% reduction.

Among input-output (IO) mode asynchronous circuits, indicating circuits are more popular and robust. However, they may not be efficient in design metrics such as cycle time, area, and power dissipation. In contrast, monotonic circuits, which are also IO mode asynchronous circuits but less explored, can potentially optimize the design metrics better than indicating circuits. Recent studies have demonstrated that monotonic circuits outperform indicating circuits in arithmetic operations like addition and multiplication. While monotonic circuits may be labeled theoretically less robust than indicating circuits, their operation is similar in practice. This article presents a novel, compact monotonic IO mode asynchronous multiplexer. The multiplexer is significant in digital circuits as it has applications across various domains including communication systems, digital signal processing, memory addressing, etc. We considered dual-rail encoding for the multiplexer and employed four-phase handshaking. Two four-phase handshaking schemes are available namely, return-to-zero (RtZ) handshaking and returnto-one (RtO) handshaking, and we considered both for this work. Compared to an optimized early output quasi-delay-insensitive multiplexer, which is derived by modifying a strongindication multiplexer and represents the best among the existing designs, the proposed monotonic multiplexer achieves a 67% (69%) reduction in latency, an 84% (84%) reduction in area, and a 66% (67%) reduction in power for RtZ (RtO) handshaking. Since the multiplexer is a small component, its effectiveness should be evaluated by integrating it into a circuit setup. In this context, we used existing multiplexers and the proposed multiplexer to realize IO mode asynchronous 32-bit carry select adders (CSLAs) while keeping the compute element, namely the full adder consistent. We estimated the design metrics of CSLAs incorporating different multiplexers, implemented using a 28-nm bulk CMOS process technology. The CSLA utilizing the proposed monotonic multiplexer achieved a 43% (44%) reduction in cycle time and a 28% (28%) reduction in area compared to the CSLA utilizing an early output quasidelay-insensitive multiplexer for RtZ (RtO) handshaking with no power penalty.

Mission-critical and safety-critical applications generally tend to incorporate triple modular redundancy (TMR) to embed fault tolerance in their physical implementations. In a TMR realization, an original function block, which may be a circuit or a system, and two exact copies of the function block are used to successfully overcome any temporary fault or permanent failure of an arbitrary function block during the routine operation. The corresponding outputs of the function blocks are majority voted using 3-input majority voters whose outputs define the outputs of a TMR realization. Hence, a 3-input majority voter forms an important component of a TMR realization. Many synchronous majority voters and an asynchronous non-delay insensitive majority voter have been presented in the literature. Recently, quasi delay insensitive (QDI) asynchronous majority voters for TMR applications were also discussed in the literature. In this regard, this paper presents a new QDI asynchronous majority voter for TMR applications, which is better optimized in area compared to the existing QDI majority voters. The proposed QDI majority voter requires 30.2% less area compared to the best of the existing QDI majority voters, and this could be useful for resource-constrained fault tolerance applications. The example QDI TMR circuits were implemented using a 32/28nm complementary metal oxide semiconductor (CMOS) process. The delay insensitive dual rail code was used for data encoding, and 4-phase return-to-zero and return-to-one handshake protocols were used for data communication.

This paper presents a novel method to identify and insert redundant logic into a combinational circuit to improve its fault tolerance without having to replicate the entire circuit as is the case with conventional redundancy techniques. In this context, it is discussed how to estimate the fault masking capability of a combinational circuit using the truth-cum-fault enumeration table, and then it is shown how to identify the logic that can introduced to add redundancy into the original circuit without affecting its native functionality and with the aim of improving its fault tolerance though this would involve some trade-off in the design metrics. However, care should be taken while introducing redundant logic since redundant logic insertion may give rise to new internal nodes and faults on those may impact the fault tolerance of the resulting circuit. The combinational circuit that is considered and its redundant counterparts are all implemented in semi-custom design style using a 32/28nm CMOS digital cell library and their respective design metrics and fault tolerances are compared.

The free vibration analysis of cyclic symmetric structures is considered as a Hermitian eigenvalue problem in semi‐complex domain using subspace iteration method is presented. The trial vectors are selected using a modified Ritz vector scheme. A modified convergence criterion which gives true error estimates which is suited for clustered eigenvalue problems is presented. Also the effect of purification of trial vectors on convergence is considered.

Multiplication is a basic arithmetic operation that is encountered in almost all general-purpose microprocessing and digital signal processing applications, and multiplication is physically realized using a multiplier. This paper discusses the physical implementation of indicating asynchronous multipliers, which are inherently elastic and are robust to timing, process, and parametric variations, and are modular. We consider the physical implementation of many weak-indication asynchronous multipliers using a 32/28-nm CMOS technology by adopting the array multiplier architecture. The multipliers are synthesized in a semi-custom ASIC-design style. The 4-phase return-to-zero (RTZ) and the 4-phase return-to-one (RTO) handshake protocols are considered for the data communication. The multipliers are realized using strong-indication or weak-indication full adders. Strong-indication 2-input AND function is used to generate the partial products in the case of both RTZ and RTO handshaking. The full adders considered are derived from different indicating asynchronous logic design methods. Among the multipliers considered, a weak-indication asynchronous multiplier utilizing the biased weak-indication full adder is found to be efficient in terms of the cycle time and the power-cycle time product with respect to both RTZ and RTO handshaking. Also, the 4-phase RTO handshake protocol is found to be preferable than the 4-phase RTZ handshake protocol for achieving enhanced optimizations in the design metrics.

Approximate ripple carry adders (RCAs) and carry lookahead adders (CLAs) are presented which are compared with accurate RCAs and CLAs for performing a 32-bit addition. The accurate and approximate RCAs and CLAs are implemented using a 32/28nm CMOS process. Approximations ranging from 4- to 20-bits are considered for the less significant adder bit positions. The simulation results show that approximate RCAs report reductions in the power-delay product (PDP) ranging from 19.5% to 82% than the accurate RCA for approximation sizes varying from 4- to 20-bits. Also, approximate CLAs report reductions in PDP ranging from 16.7% to 74.2% than the accurate CLA for approximation sizes varying from 4- to 20-bits. On average, for the approximation sizes considered, it is observed that approximate CLAs achieve a 46.5% reduction in PDP compared to the approximate RCAs. Hence, approximate CLAs are preferable over approximate RCAs for the low power implementation of approximate computer arithmetic.

The section-carry based carry lookahead adder (SCBCLA) architecture was proposed as an efficient alternative to the conventional carry lookahead adder (CCLA) architecture for the physical implementation of computer arithmetic. In previous related works, self-timed SCBCLA architectures and synchronous SCBCLA architectures were realized using standard cells and FPGAs. In this work, we deal with improved realizations of synchronous SCBCLA architectures designed in a semi-custom fashion using standard cells. The improvement is quantified in terms of a figure of merit (FOM), where the FOM is defined as the inverse product of power, delay and area. Since power, delay and area of digital designs are desirable to be minimized, the FOM is desirable to be maximized. Starting from an efficient conventional carry lookahead generator, we show how an optimized section-carry based carry lookahead generator is realized. In comparison with our recent work dealing with standard cells based implementation of SCBCLAs to perform 32-bit addition of two binary operands, we show in this work that with improved section-carry based carry lookahead generators, the resulting SCBCLAs exhibit significant improvements in FOM. Compared to the earlier optimized hybrid SCBCLA, the proposed optimized hybrid SCBCLA improves the FOM by 88.3%. Even the optimized hybrid CCLA features improvement in FOM by 77.3% over the earlier optimized hybrid CCLA. However, the proposed optimized hybrid SCBCLA is still the winner and has a better FOM than the currently optimized hybrid CCLA by 15.3%. All the CCLAs and SCBCLAs are implemented to realize 32-bit dual-operand binary addition using a 32/28nm CMOS process.

In this work, the authors consider the problem of logic minimization for a special class of Boolean networks, targeting low power implementation, using static CMOS logic. The authors start by framing a new binary minterm-value (BmV) matrix/binary max term-value (BMV) matrix for a binary 2-tuple, [mi (Mi), mj (Mj)], where HD (mi (Mi), mj (Mj)) is O(n), where n represents the support of a Boolean function. The quality of the resulting circuits, evaluated on the basis of established cost metrics for a modest 0.35mu TSMC CMOS process, demonstrate average savings in power by 14.39% for the samples mentioned in this paper, besides reduction in gate and literal count by 36.59% and 11.35% respectively, over the best of existing methods

FPGAs are prominent electronic devices used in mission-critical applications due to their reconfiguration mechanism. The mission-critical applications will be used in harsh radiation environments. Electronic devices are susceptible to single-event upsets because of radiation effects. Prior works used various traditional fault-tolerant mechanisms like...

This paper presents a new early output hybrid input encoded asynchronous full adder designed using dual-rail and 1-of-4 delay-insensitive data codes. The proposed full adder when cascaded to form a ripple carry adder (RCA) necessitates the use of a small relative-timing assumption with respect to the internal carries, which is independent of the RCA size. The forward latency of the proposed hybrid input encoded full adder based RCA is data-dependent while its reverse latency is the least equaling the propagation delay of just one full adder. Compared to the best of the existing hybrid input encoded full adders based 32-bit RCAs, the proposed early output hybrid input encoded full adder based 32-bit RCA enables respective reductions in forward latency and area by 7.9% and 5.6% whilst dissipating the same average power; in terms of the theoretically computed cycle time, the latter reports a 10.9% reduction compared to the former.

This paper investigates the application of approximate addition in digital image compression. Discrete cosine transform (DCT) is an important operation in digital image compression and we considered utilizing accurate addition and approximate addition separately while calculating the DCT. Accurate addition was performed using the accurate adder and approximate addition was performed using different approximate adders. Accurate and approximate adders were implemented in an ASIC design environment using a 32-28nm CMOS standard cell library and in a FPGA design environment using a Xilinx Artix-7 device. Error analysis has been performed to calculate mean absolute error and root mean square error of approximate adders by considering one million random input vectors. It is observed that approximate adders help to better reduce the file size of compressed images than the accurate adder. Simultaneously, the approximate adders enable reductions in design metrics compared to the accurate adder. For a FPGA implementation, an optimum approximate adder achieves 8% delay reduction and 19.7% power reduction while consuming 47.6% fewer LUTs and 42.2% fewer flip-flops compared to the accurate FPGA adder. With respect to an ASIC based implementation using standard library cells, an optimum approximate adder achieves 27.1% delay reduction, 46.4% area reduction and 50.3% power reduction compared to a high-speed accurate carry look-ahead adder.

Adder is an important datapath unit of a general-purpose microprocessor or a digital signal processor. In the nanoelectronics era, the design of an adder that is modular and which can withstand variations in process, voltage and temperature are of interest. In this context, this article presents a new robust early output asynchronous block carry lookahead adder (BCLA) with redundant carry logic (BCLARC) that has a reduced power-cycle time product (PCTP) and is a low power design. The proposed asynchronous BCLARC is implemented using the delay-insensitive dual-rail code and adheres to the 4-phase return-to-zero (RTZ) and the 4-phase return-to-one (RTO) handshaking. Many existing asynchronous ripple-carry adders (RCAs), carry lookahead adders (CLAs) and carry select adders (CSLAs) were implemented alongside to perform a comparison based on a 32/28 nm complementary metal-oxide-semiconductor (CMOS) technology. The 32-bit addition was considered for an example. For implementation using the delay-insensitive dual-rail code and subject to the 4-phase RTZ handshaking (4-phase RTO handshaking), the proposed BCLARC which is robust and of early output type achieves: (i) 8% (5.7%) reduction in PCTP compared to the optimum RCA, (ii) 14.9% (15.5%) reduction in PCTP compared to the optimum BCLARC, and (iii) 26% (25.5%) reduction in PCTP compared to the optimum CSLA.

No abstract is provided for this article.

Due to the advances in electronics design automation industry, worldwide, the integrated approach to model and emulate the single event effects due to cosmic radiation, in particular single event upsets or single event transients is gaining momentum. As of now, no integrated methodology to inject the fault in parallel to functional test vectors or to estimate the effects of radiation for a selected function in system on chip at design phase exists. In this paper, a framework, PRogrammable single Event effects Demonstrator for dIgital Chip Technologies (PREDICT) failure assessment for radiation effects is developed using a hardware platform and aided by genetic algorithms addressing all the above challenges. A case study is carried out to evaluate the frameworks capability to emulate the effects of radiation using the co-processor as design under test (DUT) function. Using the ML605 and Virtex-6 evaluation board for single and three particle simulations with the layered atmospheric conditions, the proposed framework consumes approximately 100 min and 300 min, respectively; it consumes 600 min for 3 particle random atmospheric conditions, using the 64 GB RAM, 64-bit operating system with 3.1 GHz processor based workstation. The framework output transforms the 4 MeVcm2/mg linear energy transfer to a single event transient pulse width of 2 μs with 105 amplification factor for visualisation, which matches well with the existing experimental results data. Using the framework, the effects of radiation for the co-processing module are estimated during the design phase and the success rate of the DUT is found to be 48 per cent.

At the gate level, the Kogge-Stone adder (KSA) is known to outperform many high-speed adders including other parallel prefix adders in terms of the speed performance. This paper presents a methodology to synthesize a new high-speed adder automatically, called the AHSA, using a logic synthesis tool. We describe what adder architectures can be input to a logic synthesis tool and what synthesis constraints should be specified so that the AHSA can be automatically synthesized. The AHSA is significant since it has a speed similar to that of the KSA while requiring less area and dissipating less power. In this paper, 32-bit addition serves as an example, and various adders belonging to different architectures were synthesized using a 28 nm Synopsys CMOS standard cell library. The design metrics estimated show that while the KSA has a 5.2% reduced delay than the AHSA, the AHSA occupies 29.1% less area and consumes 9.6% less power than the KSA. In terms of the figures of merit used for a digital circuit design such as power-delay product (PDP), area-delay product (ADP), and power-delay-area product (PDAP), the AHSA achieves a 4.7% reduced PDP, a 25.2% reduced ADP, and a 32.4% reduced PDAP compared to the KSA. This paper demonstrates that when speed is the key factor in an adder design, the AHSA is preferable to the KSA. Moreover, the AHSA is shown to be significantly faster than other high-speed adders at the gate level.