154 publications from this institution
In this paper, we propose a logic synthesis technique that achieves delay optimization along with simultaneous depth reduction, apart from minimizing resources for a logic tree structure. Although it is a technology-independent scheme, it is guaranteed to enable better results overall, even after the technology-mapping phase, as evident from the results obtained due to the inherent nature of the heuristic. The practical results derived by targeting a SPARTAN III FPGA logic family (XC3S50-4PQ144) show that there is an explicit delay optimization by about 9.11%, reduction in logic depth by 26.63% and decrease in resource utilization by around 38.59%, on an average, in comparison with existing methods in literature
A new majority and minority voted redundancy (MMR) scheme is proposed that can provide the same degree of fault tolerance as N-modular redundancy (NMR) but with fewer function units and a less sophisticated voting logic. Example NMR and MMR circuits were implemented using a 32/28nm CMOS process and compared. The results show that MMR circuits dissipate less power, occupy less area, and encounter less critical path delay than the corresponding NMR circuits while providing the same degree of fault tolerance. Hence the MMR is a promising alternative to the NMR to efficiently implement high levels of redundancy in safety-critical applications.
Approximate computation has emerged as a promising alternative to accurate computation, particularly for applications that can tolerate some degree of error without significant degradation of the output quality. This work analyzes the application of approximate computing for machine learning, specifically focusing on k-means clustering, one of the more widely used unsupervised machine learning algorithms. The k-means algorithm partitions data into k clusters, where k also denotes the number of centroids, with each centroid representing the center of a cluster. The clustering process involves assigning each data point to the nearest centroid by minimizing the within-cluster sum of squares (WCSS), a key metric used to evaluate clustering quality. A lower WCSS value signifies better clustering. Conventionally, WCSS is computed with high precision using an accurate adder. In this paper, we investigate the impact of employing various approximate adders for WCSS computation and compare their results against those obtained with an accurate adder. Further, we propose a new approximate adder (NAA) in this paper. To assess its effectiveness, we utilize it for the k-means clustering of some publicly available artificial datasets with varying levels of complexity, and compare its performance with the accurate adder and many other approximate adders. The experimental results confirm the efficacy of NAA in clustering, as NAA yields WCSS values that closely match or are identical to those obtained using the accurate adder. We also implemented hardware designs of accurate and approximate adders using a 28 nm CMOS standard cell library. The design metrics estimated show that NAA achieves a 37% reduction in delay, a 22% reduction in area, and a 31% reduction in power compared to the accurate adder. In terms of the power-delay product that serves as a representative metric for energy efficiency, NAA reports a 57% reduction compared to the accurate adder. In terms of the area-delay product that serves as a representative metric for design efficiency, NAA reports a 51% reduction compared to the accurate adder. NAA also outperforms several existing approximate adders in terms of design metrics while preserving clustering effectiveness.
This article describes the design of approximate array multipliers by making vertical or horizontal cuts in an accurate array multiplier followed by different input and output assignments within the multiplier. We consider a digital image denoising application and show how different combinations of input and output assignments in an approximate array multiplier affect the quality of the denoised images. We consider the accurate array multiplier and several approximate array multipliers for synthesis. The multipliers were described in Verilog hardware description language and synthesized by Synopsys Design Compiler using a 32/28-nm complementary metal-oxide-semiconductor technology. The results show that compared to the accurate array multiplier, one of the proposed approximate array multipliers viz. PAAM01-V7 achieves a 28% reduction in critical path delay, 75.8% reduction in power, and 64.6% reduction in area while enabling the production of a denoised image that is comparable in quality to the image denoised using the accurate array multiplier. The standard design metrics such as critical path delay, total power dissipation, and area of the accurate and approximate multipliers are given, the error parameters of the approximate array multipliers are provided, and the original image, the noisy image, and the denoised images are also depicted for comparison.
Literature addressing the static and dynamic analysis of turbine blades and discs is reviewed. The various formulations and solutions of linear and nonlinear vibrations of blades and discs are summarized. Experimental methods are also discussed.
Multiplication is a widely used arithmetic operation that is frequently encountered in micro-processing and digital signal processing. Multiplication is implemented using a multiplier, and recently, QDI asynchronous array multipliers were presented in the literature utilizing delay-insensitive double-rail data encoding and four-phase return-to-zero (RTZ) handshaking and four-phase return-to-one (RTO) handshaking. In this context, this article makes two contributions: (i) the design of a new asynchronous partial product generator, and (ii) the design of a new asynchronous half adder. We analyze the usefulness of the proposed partial product generator and the proposed half adder to efficiently realize QDI array multipliers. When the new partial product generator and half adder are used along with our indicating full adder, significant reductions are achieved in the design metrics compared to the optimum QDI array multiplier reported in the literature. The cycle time is reduced by 17%, the area is reduced by 16.1%, the power is reduced by 15.3%, and the product of power and cycle time is reduced by 29.6% with respect to RTZ handshaking. On the other hand, the cycle time is reduced by 13%, the area is reduced by 16.1%, the power is reduced by 15.2%, and the product of power and cycle time is reduced by 26.1% with respect to RTO handshaking. Further, the RTO handshaking is found to be preferable to RTZ handshaking to achieve slightly improved optimizations in the design metrics. The QDI array multipliers were realized using a 32/28nm complementary metal oxide semiconductor (CMOS) process technology.
A subspace iteration scheme for the Hermitian eigenvalue problem arising from analysis of cyclic symmetric structures is presented. This operates in the semi‐complex domain and its computational efficiency is demonstrated. A modified convergence checking criterion which gives better error estimates, and a new trial vector selection scheme which accelerates convergence for the Hermitian eigenvalue problem based on the Ritz method, are presented.
Structural representation and technology mapping of a Boolean function is an important problem in the design of nonregenerative digital logic circuits (also called combinational logic circuits). Library aware function manipulation offers a solution to this problem. Compact multi-level representation of binary networks, based on simple circuit structures, such as AND-Inverter Graphs (AIG) [1] [5], NAND Graphs, OR-Inverter Graphs (OIG), AND-OR Graphs (AOG), AND-OR-Inverter Graphs (AOIG), AND-XORInverter Graphs, Reduced Boolean Circuits [8] does exist in literature. In this work, we discuss a novel and efficient graph realization for combinational logic circuits, represented using a NAND-NOR-Inverter Graph (NNIG), which is composed of only two-input NAND (NAND2), NOR (NOR2) and inverter (INV) cells. The networks are constructed on the basis of irredundant disjunctive and conjunctive normal forms, after factoring, comprising terms with minimum support. Construction of a NNIG for a non-regenerative function in normal form would be straightforward, whereas for the complementary phase, it would be developed by considering a virtual instance of the function. However, the choice of best NNIG for a given function would be based upon literal count, cell count and DAG node count of the implementation at the technology independent stage. In case of a tie, the final decision would be made after extracting the physical design parameters. We have considered AIG representation for reduced disjunctive normal form and the best of OIG/AOG/AOIG for the minimized conjunctive normal forms. This is necessitated due to the nature of certain functions, such as Achilles- heel functions. NNIGs are found to exhibit 3.97% lesser node count compared to AIGs and OIG/AOG/AOIGs; consume 23.74% and 10.79% lesser library cells than AIGs and OIG/AOG/AOIGs for the various samples considered. We compare the power efficiency and delay improvement achieved by optimal NNIGs over minimal AIGs and OIG/AOG/AOIGs for various case studies. In comparison with functionally equivalent, irredundant and compact AIGs, NNIGs report mean savings in power and delay of 43.71% and 25.85% respectively, after technology mapping with a 0.35 micron TSMC CMOS process. For a comparison with OIG/AOG/AOIGs, NNIGs demonstrate average savings in power and delay by 47.51% and 24.83%. With respect to device count needed for implementation with static CMOS logic style, NNIGs utilize 37.85% and 33.95% lesser transistors than their AIG and OIG/AOG/AOIG counterparts.
The electronic structure of double perovskite Pr<sub>2</sub>MnNiO<sub>6</sub> was studied using core x-ray photoelectron spectroscopy and x-ray absorption spectroscopy. The 2p x-ray absorption spectra show that Mn and Ni are in 4+ and 2+ states respectively. Based on charge transfer multiplet analysis of the 2p XPS spectra of both ions, we find charge transfer energies [Formula: see text] of 3.5 and 2.5 eV for Ni and Mn respectively. The ground state of Ni<sup>2+</sup> and Mn<sup>4+</sup> ions reveal a higher d electron count of 8.21 and 3.38 respectively as compared to the ionic values. The partial density of states clearly show a charge transfer character of the system for U - J [Formula: see text] 2 eV. The O 1s edge absorption spectra reveal a band gap of 0.9 eV, which is close to the value estimated from analysis of Ni and Mn 2p photoemission and absorption spectra. The combined analysis of nature of spectroscopic data and first principles calculations reveal that the material is a p - d type charge transfer insulator with an intermediate covalent character according to the Zannen-Sawatzy-Allen phase diagram.
The distributed minority and majority voting based redundancy (DMMR) scheme was recently proposed as an efficient alternative to the conventional N-modular redundancy (NMR) scheme for the physical design of mission/safety-critical circuits and systems. The DMMR scheme enables significant improvements in fault tolerance and design metrics compared to the NMR scheme albeit at the expense of a slight decrease in the system reliability. In this context, this paper studies the system reliability, fault tolerance and design metrics tradeoffs in the DMMR scheme compared to the NMR scheme when the majority logic group of the DMMR scheme is increased in size relative to the minority logic group. Some example DMMR and NMR systems were realized using a 32/28nm CMOS process and compared. The results show that 5-of-M DMMR systems have a similar or better fault tolerance whilst requiring similar or fewer function modules than their counterpart NMR systems and simultaneously achieve optimizations in design metrics. Nevertheless, 3-of-M DMMR systems have the upper hand with respect to fault tolerance and design metrics optimizations than the comparable NMR and 5-of-M DMMR systems. With regard to system reliability, NMR systems are closely followed by 5-of-M DMMR systems which are closely followed by 3-of-M DMMR systems. The verdict is 3-of-M DMMR systems are preferable to implement higher levels of redundancy from a combined system reliability, fault tolerance and design metrics perspective to realize mission/safety-critical circuits and systems.
Image blending, which involves a mix of images, is used in computer graphics and photo editing. For example, two images can be blended through addition or multiplication. Usually, accurate addition or multiplication is performed to blend the images. In this paper, we discuss image blending using approximate multiplication. We show that approximate multiplication can yield visually similar blended images as accurate multiplication through an example illustration. We discuss a systematic approximation of the accurate array multiplier by introducing a series of vertical cuts in it and assign different combinations of binary values to the dangling internal inputs and dangling product bits. For an 8x8 image blending operation, our proposed approximate array multiplier is found to achieve 21 % reduction in delay, 63.3% reduction in area, and 72.3% reduction in power compared to the accurate array multiplier while yielding a visually acceptable blended image. Further, compared to a highspeed accurate multiplier that was directly synthesized using a logic synthesis tool, our proposed approximate array multiplier reports 9.7% reduction in delay, 60.6% reduction in area, and 64.7% less power. The multipliers were physically realized using a 32/28-nm CMOS technology.
This paper presents a new approximate adder architecture which when implemented on an FPGA consumes fewer logic resources compared to accurate adders of similar size and can achieve higher or comparable operating frequencies. For 32-bit addition, our approximate adder achieves a 25% reduction in the number of LUTs utilized compared to the accurate adder with no compromise on the speed performance. For 64-bit addition, our approximate adder achieves a 24% improvement in the maximum operating frequency, and a 25% reduction in the number of LUTs utilized compared to the accurate adder (post place and route on a Virtex-7 FPGA device). We also make comparisons with the FPGA-based implementations of some well-known gate-level approximate adders, and further provide insights into the error characteristics showing that the proposed approximate adder has a reduced error range.
Approximate computing is gaining increasing interest among the VLSI design community due to its potential for enabling low power, high speed, and less area while delivering acceptably correct computation results for many digital signal processing applications. In this context, this paper considers for the first time asynchronous quasi-delay-insensitive (QDI) realizations of approximate adders which are compared with some existing accurate asynchronous QDI adders based on a 32/28nm CMOS technology. The simulation results and analysis show that approximate asynchronous computing is preferable over accurate asynchronous computing when the accuracy may be traded-off to achieve optimizations in the design metrics.
A methodology for robust asynchronous implementation of Boolean functions based on the concept of duality is discussed in this paper. Importantly, this paper describes the drawbacks of an earlier related approach and suggests a novel way to overcome the problematic issues. In addition, the article illustrates how the weak-indication property can be incorporated into the modified circuit realization while preserving the robustness criterion. Lastly, this work also shows how a recently proposed robust asynchronous system configuration could be beneficial compared to the standard self-timed system architecture.
Inaccurate computing is found to be a high-speed, low-power and energy-efficient alternative to accurate computing for error-tolerant applications. In this context, this paper analyzes the usefulness of inaccurate computing for a digital image processing application, viz. digital image blending, which has been less explored. We analyze the use of inaccurate addition for image blending used in applications such as photo editing and computer graphics. For experimentation, we considered blending two digital images using accurate and inaccurate addition separately. We considered many inaccurate addition architectures which are suitable for implementation in both FPGA and ASIC design environments to perform a comparative analysis. We found that an inaccurate addition with an optimum inaccuracy produces a similar quality of blended image as obtained using accurate addition. The quality of blended images is quantified using standard metrics such as the peak signal-to-noise ratio and the structural similarity index measure. In particular, an inaccurate adder, M-HERLOA, was found to be preferable for image blending from the combined perspectives of quality of blended image, error metrics and design metrics. We implemented the accurate and inaccurate adders corresponding to an optimum inaccuracy in FPGA and ASIC design environments. We considered a Xilinx Artix-7 FPGA for an FPGA-based implementation and a 32/28 nm CMOS standard digital cell library for an ASIC type standard cell-based implementation. The results show that, for an FPGA-based implementation, M-HERLOA enables a reduction in delay by 13%, requires 50% fewer LUTs and 49% fewer registers and consumes 24.3% less on-chip power compared to the accurate high-speed FPGA adder while yielding a blended image of good quality. For an ASIC type standard cell-based implementation, M-HERLOA enables a reduction in delay by 64.6% (24.4%), requires 43% (82.4%), less area and dissipates 63% (67.8%) less power than the accurate carry ripple adder (carry look-ahead adder).
Structuring and mapping of a Boolean function is an important problem in the design of digital combinatorial circuits. Library aware constructive decomposition offers a solution to this problem. Compact multi-level representation of binary networks, based on simple circuit structures, such as AND-inverter graphs (AIG) [1] [5], NAND graphs, OR-inverter graphs (OIG), AND-XOR-inverter graphs, reduced Boolean circuits [8] does exist in literature. In this work, we discuss a novel efficient synthesis method for combinational logic circuits, represented using a NAND-inverter graph (NIG), which is composed of only two-input NAND (NAND2) and inverter (INV) cells. The networks are constructed on the basis of irredundant disjunctive normal forms, comprising terms with minimal cardinality. Construction of a NIG for a non-regenerative function in normal form would be straightforward, whereas for the opposite phase, it would be developed by considering a virtual instance of the function. However, the choice of best NIG for a given function would be based upon node count and cell count needed for actual implementation at the technology independent stage. We compare the power efficiency and delay improvement achieved by optimal NIGs over minimal AIGs and OIGs for some case studies. In comparison with functionally equivalent and redundant AIGs, NIGs report mean savings in power and delay of 33.76% and 18.57% respectively, after technology mapping with a 0.35 micron TSMC CMOS process. For a similar comparison with OIGs, NIGs demonstrate average savings in power and delay of 45.67% and 20.92% respectively.
