154 publications from this institution
A new asynchronous early output, relative-timed block carry lookahead adder (BCLA) incorporating redundant carries is proposed. Compared to the best of existing semi-custom asynchronous carry lookahead adders (CLAs) employing delay-insensitive data encoding and following a 4-phase handshaking, the proposed BCLA with redundant carries achieves 14.9% reduction in cycle time and 12.3% reduction in area with no power penalty. A hybrid variant involving a ripple carry adder (RCA) in the least significant stages i.e. BCLA-RCA is also considered that achieves 15.2% reduction in cycle time and 11.2% reduction in area over the best of existing hybrid CLARCA variants without power penalty.
Multiplication is a basic arithmetic operation that is encountered in almost all general-purpose microprocessing and digital signal processing applications, and multiplication is physically realized using a multiplier. This paper discusses the physical implementation of indicating asynchronous multipliers, which are inherently elastic and are robust to timing, process, and parametric variations, and are modular. We consider the physical implementation of many weak-indication asynchronous multipliers using a 32/28-nm CMOS technology by adopting the array multiplier architecture. The multipliers are synthesized in a semi-custom ASIC-design style. The 4-phase return-to-zero (RTZ) and the 4-phase return-to-one (RTO) handshake protocols are considered for the data communication. The multipliers are realized using strong-indication or weak-indication full adders. Strong-indication 2-input AND function is used to generate the partial products in the case of both RTZ and RTO handshaking. The full adders considered are derived from different indicating asynchronous logic design methods. Among the multipliers considered, a weak-indication asynchronous multiplier utilizing the biased weak-indication full adder is found to be efficient in terms of the cycle time and the power-cycle time product with respect to both RTZ and RTO handshaking. Also, the 4-phase RTO handshake protocol is found to be preferable than the 4-phase RTZ handshake protocol for achieving enhanced optimizations in the design metrics.
Field Programmable Gate Arrays (FPGAs) are often used in space, military, and commercial applications due to their re-programmable feature. FPGAs are semiconductor components susceptible to soft errors due to radiation effects. Fault tolerance is a critical feature for improving the reliability of electronic and computational components in high-safety applications. Triple Modular Redundancy (TMR) is electronic systems’ most commonly used fault-tolerant technique. TMR is reliable and efficient to recover the single-event upsets. However, the limitation of this technique is the area overhead. Prior work has proposed many conventional fault-tolerant approaches that have been unable to avoid area overhead. This paper introduces a novel work related to an error analysis-based technique. This technique works with an error percentage, and a preferential algorithm, which is also proposed to reduce the hardware complexity in the existing works. This technique can be applied on various types of arithmetic circuits. The proposed technique is applied to the adder circuit to verify the hardware usage, power consumption, and delay; it has been implemented on the Proasic3e 3000 FPGA. The simulated results were observed as 39.89% fewer IO cells, 47.10% fewer core cells, and 5.32% less power as compared to the TMR-based adder.
A new solution technique is proposed for the static analysis of cyclic symmetric structures, in order to reduce computational effort. Efficient node numbering methods and the selection of a basic substructure for the cyclic symmetric analysis are suggested. Extension of cyclic symmetric analysis to an axisymmetric structure subjected to unsymmetric loading also is discussed. Another new method based on load norms is presented for selection of the Fourier harmonics indices for the analysis.
With continuous decrease of device geometries in the nanoscale era of digital design, increasing importance is given to the reliability aspect of basic building blocks. In this context, this brief discusses the inherent fault tolerance capability of conventional logic gates before proceeding with the analysis of error immune property of a subset of combinational standard cells present in commercial digital libraries. The analysis has led to the following inferences: (i) Compared to complex-gate implementation, discrete-gate based realization of compound logic functions enables a mean improvement in the error resiliency metric by 68.2%, and (ii) the associated increase in area overhead for discrete-gate realizations as a trade-off for enhanced fault tolerance over complex gate implementations is found to be 51.6% on average.
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The authors wish to correct the mistakes in Figures 3a and 4a,b of the article [...]
No abstract is provided for this article.
This article presents a new distributed minority-cum-majority voting based redundancy (DMMR) scheme that is scalable and has the ability to tolerate multiple function module faults/failures. In comparison with 5-tuple, 7-tuple, and 9-tuple versions of the N-modular redundancy scheme, the proposed DMMR scheme whilst being equally fault-tolerant reports respective improvements in design metrics (i.e., figure-of-merit) by 32.5%, 180.4% and 377.4% for example ASIC-based implementations utilizing a 4×4 array multiplier as the representative function module, whilst reporting very small corresponding decreases in system reliability by just 1.21%, 1.06% and 1.08% for consideration of module reliabilities ranging from 0.9 to 0.99. The simulation results are obtained using a 32/28nm CMOS process.
We present a new approximate adder with reduced error and optimized design metrics. The proposed approximate adder is derived by modifying an existing approximate adder HERLOA and is called modified HERLOA or M-HERLOA in short. We considered a systematic modification of HERLOA to derive an optimum M-HERLOA for a digital image processing application. We calculated popular error parameters such as mean absolute error (also called mean error distance) and root mean square error of the approximate adders. We estimated the design metrics of accurate and approximate adders based on FPGA and ASIC (standard cell based) implementations. We compare the performance of accurate adder and approximate adders for an image processing application by estimating the peak signal to noise ratio and structural similarity index metric. We find that the proposed M-HERLOA reconstructs a digital image that is similar to the image reconstructed using the accurate adder. This is achieved with M-HERLOA simultaneously enabling following optimizations in design metrics compared to the accurate adder for a 32 bit addition: (i) 9.5% reduction in minimum clock period, 9.1% reduction in total on-chip power consumption, and 7 LUTs and 18 flip-flops less for a FPGA implementation, and (ii) 18% reduction in critical path delay, 26.7% reduction in average power dissipation, and 23.1% reduction in silicon area for an ASIC type implementation.
The novel design of a 8-bit decision module that forms the heart of a dynamic CMOS incrementer-cum-decrementer circuit is presented in this work. The new 8-bit decision module is designed on the basis of identifying least significant zero bit (LSZB) in the binary input stream contrary to identification of least significant one bit (LSOB), as is the case with existing approaches, to perform increment-cum-decrement operations. Further, an original cascading architecture has been proposed for building larger size incrementers-cum-decrementers based on the LSZB principle. SPICE simulations reveal that a 32-bit incrementer-cum-decrementer implemented using the proposed LSZB principle dissipates 58.6% less power than its counterpart designs based on the LSOB approach.
In this paper, the modal displacement and modal acceleration methods have been extended to the cyclic symmetry analysis in the semi-complex domain. The study of the influence of forcing frequency on the relative accuracy of the two modal methods is also made. It is shown that only few modes are sufficient to get accurate stresses in the case of modal acceleration method.
This article presents a novel approximate adder that is design-optimized and has optimized error metrics. Optimization in design translates into optimization of the design parameters such as delay, power, and area/resources, and optimization of the error metrics points to the usefulness of the proposed approximate adder for practical applications. We refer to the proposed approximate adder that is hardware optimized and having a near-normal error distribution as HOAANED, in short. We consider the implementation of HOAANED and the other approximate adders based on ASIC and FPGA design environments. We used a Xilinx Artix-7 device for a FPGA implementation, and a 32/28-nm CMOS standard digital cell library for an ASIC based implementation. To demonstrate the practical utility of HOAANED, we considered digital image processing as a practical application and performed experimentation with many images. The quality of the images reconstructed using the approximate adders was analyzed based on the peak signal-to-noise ratio (PSNR), which is used as a qualitative figure-of-merit to assess the images. It is found that HOAANED achieves an improved PSNR in comparison with the other approximate adders for image processing, and this is achieved with HOAANED simultaneously featuring optimized design metrics and error characteristics.
Mission- and safety-critical applications tend to incorporate triple modular redundancy (TMR) in their hardware implementation to reliably withstand the fault or failure of any one of the function modules during normal operation, and the function module may be a circuit or a system. In a TMR implementation, two identical copies of a function module are used in addition to the original function module, and the correct operation of at least two function modules is required. In TMR, the corresponding primary outputs of the three function modules are combined using majority voters, which determine the actual primary outputs based on the Boolean majority. Hence, the majority voter is an important component that is useful for conveying the correct operation of a TMR implementation. In the existing literature, many designs of three-input majority voters for TMR have been discussed. However, most of these correspond to the synchronous design style and just one corresponds to the bundled-data asynchronous design style, which is not delay insensitive and hence non-robust. To our knowledge, a robust delay insensitive design of the three-input majority voter has not been considered. In this context, this article presents the designs of robust quasi delay insensitive (QDI) three-input majority voters based on QDI logic synthesis methods, and analyzes which majority voters are preferable in terms of speed, power, and area. We implement example QDI TMR circuits using a QDI full adder as the function module and QDI majority voters using 32/28 nm complementary metal oxide semiconductor (CMOS) technology. The QDI TMR implementations use the delay insensitive dual rail code for data encoding, and four-phase return-to-zero and four-phase return-to-one handshake protocols for data communication.
This paper presents a synthesis framework for the important class of non-regenerative Boolean read-once functions (BROF). A two-pronged approach is adopted, where the satisfiability of the circuit functionality with minimum no. of active gates is first given priority. The gate level realizations are then translated into circuit level implementations viz., static CMOS LECTOR and stacked CMOS LECTOR styles, to evaluate the efficacy of our proposition on the basis of energy delay product (EDP) metric. Furthermore, the effect of transistor reordering on the delay of CMOS digital circuits is investigated. The SPICE based simulation results obtained for a modest 0.35mum TSMC process are promising, as it reports 41.5% savings in EDP, 10.5% reduction in power and 17.7% decrease in delay, over the best of conventional methods
This paper analyzes the usefulness of approximate addition for digital image compression. Discrete Cosine Transform (DCT) is an important operation in digital image compression. We used accurate addition and approximate addition individually while calculating the DCT to perform image compression. Accurate addition was performed using the accurate adder and approximate addition was performed using different approximate adders individually. The accurate adder and approximate adders were implemented in an application specific integrated circuit (ASIC)-type design environment using a 32–28 nm complementary metal oxide semiconductor (CMOS) standard cell library and in a field programmable gate array (FPGA)-based design environment using a Xilinx Artix-7 device. Error analysis was performed to calculate the error parameters of various approximate adders by applying one million random input vectors. It is observed that the approximate adders help to better reduce the file size of compressed images than the accurate adder. Simultaneously, the approximate adders enable reductions in design parameters compared to the accurate adder. For an ASIC-type implementation using standard cells, an optimum approximate adder achieved 27.1% reduction in delay, 46.4% reduction in area, and 50.3% reduction in power compared to a high-speed accurate carry look-ahead adder. With respect to an FPGA-based implementation, an optimum approximate adder achieved 8% reduction in delay and 19.7% reduction in power while requiring 47.6% fewer look-up tables (LUTs) and 42.2% fewer flip-flops compared to the native accurate FPGA adder.
The delay-insensitive minterm synthesis (DIMS) method facilitates a robust two-level asynchronous implementation of dual-rail encoded arbitrary combinational logic. However for multilevel realization, logic decomposition becomes indispensable. In this context, this paper describes an elegant technique of performing quasi-delay-insensitive logic decomposition based on set theoretic principles. This includes consideration of generic homogeneous and heterogeneous delay-insensitive data encoding schemes within the purview of the DIMS approach. Through the proposed set theory based logic decomposition rules, it is shown how any combinational logic specification that comprises any number of concurrent inputs can be synthesized in a multilevel fashion on the basis of the DIMS method without compromising on circuit robustness.
