EDP optimized synthesis scheme for Boolean read-once functions

This paper presents a synthesis framework for the important class of non-regenerative Boolean read-once functions (BROF). A two-pronged approach is adopted, where the satisfiability of the circuit functionality with minimum no. of active gates is first given priority. The gate level realizations are then translated into circuit level implementations viz., static CMOS LECTOR and stacked CMOS LECTOR styles, to evaluate the efficacy of our proposition on the basis of energy delay product (EDP) metric. Furthermore, the effect of transistor reordering on the delay of CMOS digital circuits is investigated. The SPICE based simulation results obtained for a modest 0.35mum TSMC process are promising, as it reports 41.5% savings in EDP, 10.5% reduction in power and 17.7% decrease in delay, over the best of conventional methods