Analysis of non-adjacency in K-maps and its impact on power consumption reduction in non-regenerative CMOS circuits

The purpose of this paper is to propose a systematic methodology for non-regenerative logic circuit design at the gate level. The traditional logic synthesis methods become ineffective in case of non-adjacent functions. In this paper, we address the reduction problem for this case by evolving a set of minimization lemmas based on the Hamming distance between the terms. Though our main emphasis has been on the satisfiability of the circuit functionality with minimum number of active gates, the approach presented here takes a viewpoint, in which all critical design metrics are investigated with the primary goal of reducing the dynamic power consumption of the circuit. The SPICE simulation results obtained on the basis of 0.5/spl mu/m CMOS technology are promising, as they report minimization in average power consumption by about 30 % for the examples cited, along with a substantial improvement in the figure of merit (FoM) of the circuit, in comparison with that obtainable using conventional approaches.