A current-mode DTCNN universal chip

The paper describes an analog current mode realization of Discrete-Time Cellular Neural Networks (DTCNNs) with high cell density, which have local analog and local logic memory. Hence, some important parts of the CNN Universal Machine concept are implemented. The computation speed can be adjusted simply to the application by changing the clock rate. The circuit components are described in detail and SPICE level 2 simulation results are given for the ORBIT 2.0 /spl mu/m process. A layout has been designed for a chip with 12 by 12 cells on a square grid realizing a one-neighborhood with 9 feedback and 9 control coefficients. The cell size is 619 /spl mu/m by 425 /spl mu/m and the simulated speed is between 1 MHz and 10 MHz depending on the minimum value of the state current. For the latter this leads to a simulated performance of 25.9 10/sup 9/ XPS for a single chip operation with an effective area of 0.379 cm/sup 2/ and a worst case power consumption of 0.86 W. Another important feature of the chip is its capability for a spatial cascaded connection.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>