VLSI implementation of a reconfigurable cellular neural network containing local logic (CNNL)

K. Halonen; V. Porra; T. Roska; Leon O Chua

doi:10.1109/cnna.1990.207526

Abstract

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A new integrated circuit cellular neural network implementation having digitally or continuously selectable template coefficients is presented. Local logic and memory is added into each cell providing a simple dual computing structure (analog and digital). The variable-gain operational transconductance amplifier (OTA) is used as voltage controlled current sources to program the weighting factors of the template elements. A 4-by-4 CNN circuit is realized using the 2 mu m analog CMOS-process. The circuit with different template configurations has been simulated with HSPIC.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>

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VLSI implementation of a reconfigurable cellular neural network containing local logic (CNNL)

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