154 publications from this institution
The aim of this paper is to analyze the impact of local and global indication on a self-timed system architecture. Towards this end, we investigate the effect of these two indicating frameworks with respect to a 32-bit self-timed carry-ripple adder, constructed using a cascade of self-timed dual-bit adder modules. In both cases, the self-timed ripple carry adder corresponds to weak-indication. We consider the analysis from the perspective of both homogeneous and heterogeneous encoding of data, employing unordered delay-insensitive codes. The simulation results reveal that global indication benefits in terms of minimizing the power and area parameters while reporting a performance advantage over local indication.
This paper presents a novel Fault-tolerant design i.e., redundancy strategy based on Approximate Computing, which we call FAC. Conventionally, triple modular redundancy (TMR) has been widely used to guarantee 100% tolerance to any single fault or failure of a processing unit where the processing unit may be a circuit or system. However, TMR results in more than 200% overhead in area and power compared to a single processing unit. To reduce the overheads in design metrics associated with TMR, alternative redundancy approaches were presented in the literature but they guarantee only partial or moderate fault tolerance. Nevertheless, among these alternative redundancy approaches, the majority voter-based reduced precision redundancy (MVRPR) may be useful for naturally error-resilient applications like digital signal processing which is commonly used in space systems. The proposed FAC is ideally suited for error-resilient applications but unlike MVRPR which guarantees only a moderate fault tolerance, FAC guarantees a 100% tolerance to any single fault or failure of a processing unit like TMR. We considered TMR, MVRPR, and FAC to comparatively evaluate their performance for a digital image processing application. The image processing results obtained demonstrate the usefulness of FAC. Further, for a physical implementation using a 28-nm CMOS technology, FAC achieves a 15.3% reduction in delay, 19.5% reduction in area, and a 24.7% reduction in power compared to TMR, and an 18% reduction in delay, 5.4% reduction in area, and 11.2% reduction in power compared to MVRPR.
