Approximate quasi-delay-insensitive asynchronous adders: Design and analysis

Approximate computing is gaining increasing interest among the VLSI design community due to its potential for enabling low power, high speed, and less area while delivering acceptably correct computation results for many digital signal processing applications. In this context, this paper considers for the first time asynchronous quasi-delay-insensitive (QDI) realizations of approximate adders which are compared with some existing accurate asynchronous QDI adders based on a 32/28nm CMOS technology. The simulation results and analysis show that approximate asynchronous computing is preferable over accurate asynchronous computing when the accuracy may be traded-off to achieve optimizations in the design metrics.