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The advent of high-bandwidth DRAMs poses a number of new challenges for test and characterization. This paper describes a collection of techniques that were used in the design and characterization of a new DRAM architecture with 500 MHz I/O signals. Methods of fixturing and calibration are presented for achieving system accuracies of better than 100 ps. Laboratory techniques for measuring critical circuit parameters such as path delay, clock jitter, current source strength, and pin capacitances are shown as well. These techniques, along with on-chip test logic, which allows the DRAM core to be tested using conventional low-speed memory test equipment, enable full characterization of high bandwidth memories.
An architecture for a single-chip functional tester which reduces the cost of testing application-specific integrated circuits (ASICs) is presented. The data generator/receiver (DGR) contains a large RAM to store the test vectors, an address sequencer for implementing simple testing loops, and a flexible set of drivers/receivers for the device-under-test (DUT) pins. A prototype design has been fabricated in 3-/spl mu/m CMOS double-level-metal technology, and contains 65 K transistors in a 9.2/spl times/7.9-mm/SUP 2/ die. A minimum operating cycle time of 90 ns (11 MHz), and a power dissipation of 300 mW was obtained for 5-V operation. A 2-/spl mu/m version of this design, just a shrink of the original chip, has been fabricated and operates over 16 megavector/s.
In this paper, a global clock network that incor- porates standing waves and coupled oscillators to distribute a high-frequency clock signal with low skew and low jitter is described. The key design issues involved in generating standing waves on a chip are discussed, including minimizing wire loss within an available technology. A standing-wave oscillator, which is a distributed oscillator that sustains ideal standing waves on lossy wires, is introduced. A clock grid architecture comprised of coupled standing-wave oscillators and differential low-swing clock buffers is presented, along with a compact circuit model for networks of oscillators. The measured results for a prototyped standing-wave clock grid operating at 10 GHz and fabricated in a 0.18- m 6M CMOS logic process are presented. A technique is proposed for on-chip skew measurements with subpicosecond precision.
Full chip mixed-signal validation requires simulating the entire design through a large number of test vectors, which makes fast, event-based Verilog models of analog circuits essential. We describe an extensible approach to creating these models that maps continuous signals into piecewise linear waveforms by creating analog events which contain a value and slope. By breaking analog circuits into sub-blocks with mostly unidirectional ports, we avoid explicit time integration, thus fitting well into an event-driven digital framework. The result is Verilog analog functional models that are pin-accurate, fast to simulate and capture the key dynamics in analog circuits. A 2.5V-1.8V buck converter and 1GHz PLL models are demonstrated.
A global clock network that incorporates standing waves and coupled oscillators to distribute a high-frequency clock signal with low skew and low jitter is described. The key design issues involved in generating standing waves on a chip are discussed, including minimizing wire loss within an available technology. A standing-wave oscillator, which is a distributed oscillator that sustains ideal standing waves on lossy wires, is introduced. A clock grid architecture comprised of coupled standing-wave oscillators and differential low-swing clock buffers is presented, along with a compact circuit model for networks of oscillators. The measured results for a prototyped standing-wave clock grid operating at 10 GHz and fabricated in a 0.18-μm 6M CMOS logic process are presented. A technique is proposed for on-chip skew measurements with subpicosecond precision.
Author(s): Amat, Fernando; Moussavi, Farshid; Horowitz, Mark | Abstract: In recent years there has been increasing interest in using cryo TEM tomography to study cells in close to their native environment. One limitation of this technique is the relatively low signal to noise ratio in each of the TEM images, since the total electron dose through the sample must be constrained to limit structure damage to the cell. Even with gold markers added to the sample, robust automatic alignment of the TEM slice data for reconstruction remains difficult. We have tried to address this problem by leveraging recent work in probabilistic analysis, and have constructed a prototype alignment system using Markov random fields (MRF s) for alignment, and robust optimization methods for projective model estimation. With markers, there are three basic steps required to align the TEM dataset: marker feature identification, correspondence and tracking of these features throughout the image set, and projective model estimation from these feature tracks. In our framework, features are extracted initially using standard template matching techniques like cross correlation. Feature correspondence and tracking is accomplished by constructing a Markov random field (MRF) probabilistic model where contour labels are random variables which take on values of candidate marker feature locations. We use mutual information and the relative geometric positions to estimate a priori marker correspondence probabilities between two images. An approximate probabilistic inference technique called loopy belief propagation (LBP) is then used to calculate the maximum a posteriori assignment of features to contours in the image set. In this technique, rather than a joint distribution (whose complexity is exponential in the number of random variables), a collection of singleton and pairwise distributions is maintained in a special data structure. This data structure contains cycles, and is called a cluster graph. The a priori estimates for these distributions (initial beliefs) are refined by belief propagation, until they converge to roughly the true pairwise distributions (final beliefs). The correspondences of candidate markers to contours are taken directly from these beliefs. Errors in the correspondence are possible due to feature location mistakes as well as inaccurate inference results. Therefore, the projective model estimation uses a robust fitting method as opposed to least squares (the traditionally applied fitting) and is tolerant to outliers. Once we have an estimate of the projective model, the model is iterated using expectation maximization (EM) to re-estimate perceived outliers with improved reprojection data from the current model. This iteration is performed as many times as necessary before a stopping criterion is satisfied, but in our example a small number of iterations is needed (often only one).This robust framework has allowed us to fully automatically recover dozens of contours (both complete and piecewise) with subpixel accuracy from several challenging cryo datasets of bacteria Caulobacter crescentus. The results were used to create 3D reconstructions comparable to results previously obtainable only by extensive manual intervention.
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