A Verilog piecewise-linear analog behavior model for mixed-signal validation

Full chip mixed-signal validation requires simulating the entire design through a large number of test vectors, which makes fast, event-based Verilog models of analog circuits essential. We describe an extensible approach to creating these models that maps continuous signals into piecewise linear waveforms by creating analog events which contain a value and slope. By breaking analog circuits into sub-blocks with mostly unidirectional ports, we avoid explicit time integration, thus fitting well into an event-driven digital framework. The result is Verilog analog functional models that are pin-accurate, fast to simulate and capture the key dynamics in analog circuits. A 2.5V-1.8V buck converter and 1GHz PLL models are demonstrated.