Error Control and Limit Cycle Elimination in Event-Driven Piecewise Linear Analog Functional Models

Real number modeling of analog circuits in hardware description languages (HDLs) has become more common as a part of mixed-signal SoC validation. We propose two methods that both improve the fidelity and simulation speed, and make the event-driven, piecewise linear (PWL) analog functional models easier to write. First we use the accuracy set by users to dynamically determine when a new output segment should be emitted, which is computed without any iteration. This capability allows designers to trade accuracy for simulation speed of analog models without any time-consuming model calibration/error estimation, and creates models which generate events only when needed to maintain output accuracy. We next extend this method to eliminate limit-cycle oscillations that occur when simulating circuits with continuous-time feedback in a discrete-time event simulator. Handling this feedback efficiently allows the user to create the system model from simpler component models. The performance of this modeling approach is demonstrated on various analog filter models, an operational amplifier, and a high-speed, wireline transceiver system, and is 3.1 $\times$ faster than an optimally-chosen, fixed-time step simulation for the transceiver.