Publications

Hydroxychloroquine and chloroquine for survival in COVID-19: an international collaborative meta-analysis of randomized trials

An international collaborative meta-analysis on mortality in all ongoing or completed randomized clinical trials evaluating hydroxychloroquine or chloroquine for COVID-19

An area-efficient minimum-time FFT schedule using single-ported memory

FFT design requires an exhaustive recoupling of data across successive stages of computation. The resulting memory access patterns have constantly-changing strides, making it hard to interleave the data for reliable conflict-free access of operand pairs. We modify an existing method of "swizzling" data locations so as to guarantee conflict-free access within any given stage and, with minimal support for buffering, we provide conflict-free access across the boundaries of adjoining stages as well. As a result, implementations that would naively require either a fully-associative, or at the very least a multiported register file, can be implemented using four single-ported banks of memory per butterfly unit, plus one bypass buffer. Because fewer ports means less area, and given that a butterfly must read two inputs and write two results for each cycle of operation, this solution should represent the least-area memory configuration for a resource-constrained FFT. Using this scheme, we show examples including a minimal one-butterfly FFT having 9% less area versus a competing equal-performance design and 20% better throughput versus a competing equal-area design.

Reporting of Systematic Reviews: The Challenge of Genetic Association Studies

We have read with great

Improving Energy Efficiency of CGRAs with Low-Overhead Fine-Grained Power Domains

To effectively minimize static power for a wide range of applications, power domains for coarse-grained reconfigurable array (CGRA) architectures need to be more fine-grained than those found in a typical application-specific integrated circuit. However, the special isolation logic needed to ensure electrical protection between off and on domains makes fine-grained power domains area- and timing-inefficient. We propose a novel design of the CGRA routing fabric that reduces the area overhead of power domain boundary protection from around 9% to less than 1% without incurring any extra timing delay from the isolation cells. Conventional Unified Power Format based flow for power domain boundary protection does not support this design choice. Therefore, we create our own compiler-like passes that iteratively introduce the needed design changes, and formally verify the transformations using methods based on satisfiability modulo theories. These passes also let us optimize how we handle test and debug signals through the off tiles in the CGRA. Using our framework, we add power domains to a CGRA that we designed and taped out. The CGRA has 32 × 16 processing element and memory tiles and 4-MB secondary memory. We address the implementation challenges encountered due to the introduction of fine-grained power domains, including the addressing of the CGRA tiles, the power grid design, well substrate connections, and distribution of global signals. Our CGRA achieves up to 83% reduction in leakage power and 26% reduction in total power versus an identical CGRA without multiple power domains, for a range of image processing and machine learning applications.

Evaluating programmable architectures for imaging and vision applications

Algorithms for computational imaging and computer vision are rapidly evolving, and hardware must follow suit: the next generation of image signal processors (ISPs) must be “programmable” to support new algorithms created with high-level frameworks. In this work, we compare flexible ISP architectures, using applications written in the Darkroom image processing language. We target two fundamental architecture classes: programmable in time, as represented by SIMD, and programmable in space, as typified by coarse grain reconfigurable array architectures (CGRA). We consider several optimizations on these two base architectures, such as register file partitioning for SIMD, bus based routing and pipelined wires for CGRA, and line buffer variations. After these optimizations on average, CGRA provides 1.6x better energy efficiency and 1.4x better compute density versus a SIMD solution, and 1.4x the energy efficiency and 3.1x the compute density of an FPGA. However the cost of providing general programmability is still high: compared to an ASIC, CGRA has 6x worse energy and area efficiency, and this ratio would be roughly 10x if memory dominated applications were excluded.

Estimates of SARS-CoV-2 Infections and Population Immunity After the COVID-19 Pandemic in Austria: Analysis of National Wastewater Data

Abstract Background Postpandemic surveillance data on coronavirus disease 2019 (COVID-19) infections may help inform future public health policies regarding severe acute respiratory syndrome coronavirus 2 (SARS-CoV-2) testing, vaccinations, or other COVID-19 measures. We estimate the total SARS-CoV-2 infections in Austria after the end of the pandemic from wastewater data and utilize these estimates to calculate the average national levels of SARS-CoV-2 infection protection and COVID-19 death protection. Methods We estimated the total SARS-CoV-2 infections in Austria after the end of the pandemic (5 May 2023, per World Health Organization) up to May 2024 from wastewater data using a previously published model. These estimates were used in an agent-based model (ABM) to estimate average national levels of SARS-CoV-2 infection protection and COVID-19 death protection, based on waning immunity estimates of infections and vaccination in previous literature. Results We estimate approximately 3.2 million infections between 6 May 2023 and 23 May 2024, with a total of 17.8 million infections following 12 May 2020. The ABM estimates that the national average death protection was approximately 82% higher in May 2024 than before the pandemic. This represents a relative decrease of 8% since May 2023. It also shows that 95% of people in Austria were infected with SARS-CoV-2 at least once by May 2024. National infection protection remained relatively low after the onset of Omicron. Conclusions These findings should be considered for public health decisions on SARS-CoV-2 testing practices and vaccine booster administrations.

Gene expression profiling for individualized breast cancer chemotherapy: success or not?

Expanding the data Ark: an attempt to make the data from highly cited social science papers publicly available

Access to scientific data can enable independent reuse and verification; however, most data are not available and become increasingly irrecoverable over time. This study aimed to retrieve and preserve important datasets from 160 of the most highly-cited social science articles published between 2008–2013 and 2015–2018. We asked authors if they would share data in a public repository—the Data Ark—or provide reasons if data could not be shared. Of the 160 articles, data for 117 (73%, 95% CI [67%–80%]) were not available and data for 7 (4%, 95% CI [0%–12%]) were available with restrictions. Data for 36 (22%, 95% CI [16%–30%]) articles were available in unrestricted form: 29 of these datasets were already available and 7 datasets were made available in the Data Ark. Most authors did not respond to our data requests and a minority shared reasons for not sharing, such as legal or ethical constraints. These findings highlight an unresolved need to preserve important scientific datasets and increase their accessibility to the scientific community.

Opportunities for optics in integrated circuits applications

Optics potentially addresses two key problems in electronic chips and systems: interconnects and timing. Short optical pulses (e.g., picoseconds or shorter) offer particularly precise timing. Results are shown for optical and electrical four-phase clocking, with <1 ps rms jitter for the optical case.

Evaluation of charge recovery circuits and adiabatic switching for low power CMOS design

A technique called charge recovery or adiabatic switching has been proposed to trade speed for energy consumption in CMOS circuits. We compare the speed/power of charge recovery to standard CMOS logic operating at different supply voltages and demonstrate that the overhead of charge recovery limits the overall power savings. In almost all cases, voltage scaled CMOS dissipates less power for the same level of performance.

The Frankencamera

Although there has been much interest in computational photography within the research and photography communities, progress has been hampered by the lack of a portable, programmable camera with sufficient image quality and computing power. To address this problem, we have designed and implemented an open architecture and API for such cameras: the Frankencamera. It consists of a base hardware specification, a software stack based on Linux, and an API for C++. Our architecture permits control and synchronization of the sensor and image processing pipeline at the microsecond time scale, as well as the ability to incorporate and synchronize external hardware like lenses and flashes. This paper specifies our architecture and API, and it describes two reference implementations we have built. Using these implementations we demonstrate six computational photography applications: HDR viewfinding and capture, low-light viewfinding and capture, automated acquisition of extended dynamic range panoramas, foveal imaging, IMU-based hand shake detection, and rephotography. Our goal is to standardize the architecture and distribute Frankencameras to researchers and students, as a step towards creating a community of photographer-programmers who develop algorithms, applications, and hardware for computational cameras.

Author response for "Reducing bias in secondary data analysis via an Explore and Confirm Analysis Workflow (ECAW): a proposal and survey of observational researchers"

JAMA

JAMA

Cascade: An Application Pipelining Toolkit for Coarse-Grained Reconfigurable Arrays

While coarse-grained reconfigurable arrays (CGRAs) have emerged as promising programmable accelerator architectures, they require automatic pipelining of applications during their compilation flow to achieve high performance. Current CGRA compilers either lack pipelining altogether resulting in low application performance, or perform exhaustive pipelining resulting in high power and resource consumption. We address these challenges by proposing Cascade, an end-to-end open-source application compiler for CGRAs that achieves both state-of-the-art performance and fast compilation times. The contributions of this work are: (1) a novel post place-and-route (PnR) application pipelining technique for CGRAs that accounts for interconnect hop delays during pipelining but in a unique way that avoids cyclic scheduling and place-and-route, (2) a register resource usage optimization technique that leverages the scheduling logic in CGRA memory tiles to minimize the number of register resources used during pipelining, and (3) an automated CGRA timing model generator, an application timing analysis tool, and a large set of existing and novel application pipelining techniques integrated into an end-to-end compilation flow. Cascade achieves 8 -34× lower critical path delay and 7 -190× lower energy-delay product (EDP) across a variety of dense image processing and machine learning workloads, and 3 -5.2× lower critical path delay and 2.5 -5.2× lower EDP on sparse workloads, compared to a compiler without pipelining. Cascade mitigates the performance and energy-efficiency drawbacks of existing CGRA compilers, and enables further research into CGRAs as flexible, yet competitive accelerator architectures.

Integrated Regulation for Energy-Efficient Digital Circuits

Despite their use in analog or mixed-signal applications, the high power overheads of traditional linear regulators (both series and shunt) have precluded their successful adoption in regulating the supply of energy-efficient digital circuits. In this paper, we show that linear regulation can in fact reduce the effective supply impedance of digital circuits without increasing their total power dissipation. Achieving this goal requires minimizing the static power dissipation of the regulator, leading to a push-pull topology (similar to the regulators demonstrated by Wu and Sanders, 2001, Poon et al, 1999, and Intersil, 1998) with comparator-based feedback and a switched source-follower output stage. Measured results from a regulator implemented in a 65 nm SOI test-chip verify that by using these techniques, regulation reduces the effective supply noise by ~30% while also enabling a slight decrease (1.4%) in total power dissipation.

Architectural support for copy and tamper resistant software

Although there have been attempts to develop code transformations that yield tamper-resistant software, no reliable software-only methods are known. This paper studies the hardware implementation of a form of execute-only memory (XOM) that allows instructions stored in memory to be executed but not otherwise manipulated. To support XOM code we use a machine that supports internal compartments---a process in one compartment cannot read data from another compartment. All data that leaves the machine is encrypted, since we assume external memory is not secure. The design of this machine poses some interesting trade-offs between security, efficiency, and flexibility. We explore some of the potential security issues as one pushes the machine to become more efficient and flexible. Although security carries a performance penalty, our analysis indicates that it is possible to create a normal multi-tasking machine where nearly all applications can be run in XOM mode. While a virtual XOM machine is possible, the underlying hardware needs to support a unique private key, private memory, and traps on cache misses. For efficient operation, hardware assist to provide fast symmetric ciphers is also required.

Indirect comparisons: the mesh and mess of clinical trials