Publications

This article presents an open-source framework for emulating mixed-signal chip designs on a field-programmable gate array (FPGA). It includes a Python-based synthesizable model generator for mixed-signal blocks (msdsl), a fixed-point and floating-point synthesizable SystemVerilog library for representing real numbers (svreal), and a Python-based tool that generates emulator control infrastructure and automates the FPGA build process (anasymod). The framework includes features for efficiently modeling analog dynamics, nonlinearity, and noise, often making use of compile-time caching to reduce the required computational resources of the FPGA. We demonstrate the framework’s generality by discussing three applications: 1) a high-speed link receiver (DragonPHY); 2) a firmware-controlled flyback converter; and 3) an NFC-powered chip. Our framework makes it easy to emulate these systems, while providing runtimes 2–3 orders of magnitude faster than CPU simulations with real-number functional models.

Packet monitoring arguably needs the flexibility of open architectures and active networking. A significant challenge in the design of open packet monitoring systems is how to effectively strike a balance between flexibility, safety and performance. In this paper we investigate the performance of FLAME, a system that emphasizes flexibility by allowing applications to execute arbitrary code for each packet received. Our system attempts to achieve high performance without sacrificing safety by combining the use of a type-safe language, lightweight run-time checks, and fine-grained policy restrictions. Experiments with our prototype implementation demonstrate the ability of our system to support representative application workloads on Gbit/s links. Such performance indicates the overall efficiency of our approach; more narrowly targeted experiments demonstrate that the overhead required to provide safety is acceptable.

A dual-loop CDR can be viewed as a simple phase-estimator. Different estimators can be built by changing the phase DAC control logic. Three different 0.13μm estimators for a 3Gb/s serial link are presented. These estimators address dual-loop CDR limitations including lock time, frequency range, and jitter tolerance in non-mesochronous systems

The high accuracy of deep neural networks (NNs) has led to the development of NN accelerators that improve performance by two orders of magnitude. However, scaling these accelerators for higher performance with increasingly larger NNs exacerbates the cost and energy overheads of their memory systems, including the on-chip SRAM buffers and the off-chip DRAM channels.

Collections of terms in PubMed with frequency analysis and etymological definitions -- Data supplements for the manuscript "Hypothesis, analysis and synthesis, it's all Greek to me" by Ioannis Iliopoulos, Sophia Ananiadou, Antoine Danchin, John PA Ioannidis, Peter D Katsikis, Christos A Ouzounis, Vasilis J Promponas (eLife: 8, e43514) (2019).<br>Data Supplement (DS): File 1 (DS01): The 243 words that appeared in at least one million PubMed records as of July 28, 2018. The words are ranked by number of appearances (second column). File 2 (DS02): The 172 words with rich meaning (that is, nouns [NN, NNS], adjectives [JJ, JJR] and verb forms [VBD, VBG, VBN, VBP, VBZ]) that appeared in at least one million PubMed records as of July 28, 2018. File 3 (DS03): The 152 words with rich meaning (that is, nouns [NN, NNS], adjectives [JJ, JJR] and verb forms [VBD, VBG, VBN, VBP, VBZ]) and four or more characters that appeared in at least one million PubMed records as of July 28, 2018. File 4 (DS04): A search string containing the 152 words with rich meaning (that is, nouns, adjectives and verb forms) and four or more characters that appeared in at least one million PubMed records as of July 28, 2018.

When the International Technology Roadmap for Semiconductors organization announced its final roadmap in 2016, it was widely heralded as the official end of Moore's law [ITRS, 2016]. As we write this, 7 nm technology is still projected to provide cheaper transistors than current technology, so it isn't over just yet. But after decades of transistor scaling, the ITRS report revealed at least modest agreement across the industry that cost-effective scaling to 5 nm and below was hardly a guarantee.

Abstract Background Data on the rate and severity of SARS-CoV-2 reinfections in real-world settings are scarce and the effects of vaccine boosters on reinfection risk are unknown. Methods In a retrospective cohort study, registered SARS-CoV-2 laboratory-confirmed Vojvodina residents, between March 6, 2020 and October 31, 2021, were followed for reinfection ≥90 days after primary infection. Data were censored at the end of follow-up (January 31, 2022) or death. The reinfection risk was visualized with Kaplan-Meier plots. To examine the protective effect of vaccination, the subset of individuals with primary infection in 2020 (March 6-December 31) were matched (1:2) with controls without reinfection. Findings Until January 31, 2022, 13,792 reinfections were recorded among 251,104 COVID-19 primary infections (5.49%). Most reinfections (86.8%) were recorded in January 2022. Reinfections were mostly mild (99.2%). Hospitalizations were uncommon (1.8% vs . 3.70% in primary infection) and COVID-19 deaths were very rare (n=20, case fatality rate 0.15%). The overall incidence rate of reinfections was 5.99 (95% CI 5.89-6.09) per 1,000 person-months. The reinfection risk was estimated as 0.76% at six months, 1.36% at nine months, 4.96% at 12 months, 16.7% at 15 months, and 18.9% at 18 months. Unvaccinated (OR=1.23; 95%CI=1.14-1.33), incompletely (OR=1.33; 95%CI=1.08-1.64) or completely vaccinated (OR=1.50; 95%CI=1.37-1.63), were modestly more likely to be reinfected compared with recipients of a third (booster) vaccine dose. Interpretation SARS-CoV-2 reinfections were uncommon until the end of 2021 but became common with the advent of Omicron. Very few reinfections were severe. Boosters may modestly reduce reinfection risk.