A dual-loop CDR can be viewed as a simple phase-estimator. Different estimators can be built by changing the phase DAC control logic. Three different 0.13μm estimators for a 3Gb/s serial link are presented. These estimators address dual-loop CDR limitations including lock time, frequency range, and jitter tolerance in non-mesochronous systems
Chloe Pek Sang Tang, Professor Gregory Lip, Terry McCormack, Alexander R. Lyon, Peter Hillmen, Sunil Iyengar, Nicolás Martínez‐Calle, Nilima Parry‐Jones, Piers Patten, Anna Schuh, Renata Walewska
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