A single chip LSI high-speed functional tester

An architecture for a single-chip functional tester which reduces the cost of testing application-specific integrated circuits (ASICs) is presented. The data generator/receiver (DGR) contains a large RAM to store the test vectors, an address sequencer for implementing simple testing loops, and a flexible set of drivers/receivers for the device-under-test (DUT) pins. A prototype design has been fabricated in 3-/spl mu/m CMOS double-level-metal technology, and contains 65 K transistors in a 9.2/spl times/7.9-mm/SUP 2/ die. A minimum operating cycle time of 90 ns (11 MHz), and a power dissipation of 300 mW was obtained for 5-V operation. A 2-/spl mu/m version of this design, just a shrink of the original chip, has been fabricated and operates over 16 megavector/s.