Current integrating receivers for high speed system interconnects

This paper presents a high speed receiver design that utilizes current integration in order to increase its noise immunity. The integration of current on a capacitor based on the incoming signal voltage effectively averages the incoming signal over its valid time period, therefore filtering out high frequency noise. An experimental design illustrating the concept has been fabricated in a 1.2 /spl mu/m CMOS technology. The receiver dissipates 2.7 mW of power operating from a 5-V supply, achieves error free operation at a clock frequency of 250 MHz, and occupies 60/spl times/450 /spl mu/m/sup 2/ of silicon area.