A single-chip, functional tester for VLSI circuits

A single-chip functional tester for VLSI circuits that integrates the vector memory, the error memory, a decompressor, and 16 sets of independently controlled pin electronics on a 9.0*9.4-mm chip is described. The device contains over 200 K transistors and is fabricated using a 1.6- mu m CMOS technology. The integrated pin electronics support a per-pin tester architecture, allowing the transitions for each pin to be independently adjusted to better than 1 ns. The chip dissipates less than 0.75 W running at 25 M vectors/s. By integrating all tester functions on a single chip, it is possible to build all extremely compact tester. A 256-pin tester requires only 16 chips. This size makes it possible to reduce the length of the transmission line between the device under test and the tester to under 10 cm, minimizing signal reflections and enabling the delivery of high-fidelity waveforms.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>