Low power high-speed current comparator using 130nm CMOS technology

Current comparators are extensively used in current steering (CS) digital to analog data converters (DAC) which are used in almost all digital devices now days. With the growing demand for higher operation speed and longer battery life, it is crucial that the propagation delay and the power consumption of current comparator circuitry be further reduced. To this view in this research, a low power and high-speed CMOS current comparator using a Wilson current mirror circuitry at input stage have been presented. The circuit has been designed using Mentor Graphic — CEDEC's Silterra Design Kit based on 0.13 μm standard CMOS process and layout have been presented. The achieved propagation delay of the designed comparator is 0.37ns. The designed circuit consumes 0.3461mW and 0.1915mW power when the difference in input current is ±0.4μA and ±0.1μA respectively. Through performance comparison with converters presented in previous researches, it has been shown that the proposed current converter provides the lowest propagation delay and lowest power consumption for input current difference of ±0.4μA and ±0.1μA. Thus, this research represents a significant improvement of the performance of current comparator circuitry.