Low power digital design using modified GDI method

GDI (gate diffusion input) based technique for low power combinational logic circuit design has been elaborately discussed and the advantage of this design style over static CMOS (SC) implementation and pass-transistor logic (PTL), with regard to power consumption, delay and area complexity is also described in recent literature (Morgenshtein, 2002). In this paper, we propose a couple of new GDI based cell designs, which are found to be much more power efficient in comparison with existing GDI based cell functionality. The significance of these designs is substantiated by the simulation results obtained for a 0.35 muM TSMC CMOS technology, where an improvement in power efficiency of the order of 2-3times is reported in the pre-layout stage for some widely used important digital arithmetic circuits