RETRACTED: Design of 8-bit Dynamic CMOS Priority Resolvers based on Active- High and Active-Low Logic

A couple of new dynamic CMOS based designs of an 8-bit priority resolver corresponding to activehigh and active-low logic are presented in this paper. The proposed designs result from modifications to an 8- bit priority resolver designed by Huang and Chang [15], which pertains to active-high logic. Compared to Huang and Chang’s original 8-bit CMOS priority resolver, the modified designs achieve 4× mean reduction in power dissipation, and report average improvement in the power-delay product by 43%. The simulation results were obtained using Tanner tools (TSPICE), and correspond to a 0.25μm CMOS process technology.