Design of high‐speed, high‐density CNNS in cmos technology

Abstract An analogue VLSI circuit architecture for the CMOS implementation of cellular neural networks (CNNs) is presented. It is based exclusively on the use of small capacitors and operational transconductance amplifiers operating in continuous time. Integrated circuit implementations of this architecture are very well suited for processing applications requiring large array size and high speed. We describe a systematic design approach for those circuits and present the design, fabrication and testing of two chips. These chips are used for connected component detection applications and are the first working integrated circuit implementation of a CNN. They contain 2000 transistors and have been fabricated using 2 μm CMOS technology. the density is 32 cells per square millimetre of silicon and the time constant of the processing is of the order of 10 −7 s. Experimental results of static and dynamic tests are given, including a complete image‐processing example.