Circuit techniques for large CSEA SRAMs

The CMOS-storage emitter-access (CSEA) memory cell offers faster access than the MOS cells used in conventional BiCMOS SRAMs but using it in large memory arrays poses several problems. Novel BiCMOS circuit approaches to address the problems of decoding power, electronic noise, level translation, and write disturbance are described. Results on a 64-kb CSEA SRAM using these techniques are reported. The device, fabricated in an 0.8- mu m BiCMOS technology, achieves read access and write pulse time of less than 4 ns while dissipating 1.7 W at a case temperature of 70 degrees C.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>