A 4-ns BiCMOS translation-lookaside buffer

A 64-entry fully associative TLB (translation-lookaside buffer) with a pin-to-pin translation delay of 3.6 ns is described. This translation speed is achieved by using BiCMOS content-addressable memory (CAM) and SRAM arrays wherein small signal swings are maintained throughout the critical translation path. A BiCMOS CAM cell that uses a single bipolar translator to drive the match line is introduced. The TLB has been integrated as a stand-alone chip in an 0.8- mu m BiCMOS technology. The circuit operates from a 5.2-V supply with ECL-compatible input and output levels. The power dissipation (excluding the power dissipated in the physical address output buffers) is less than 600 mW.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>