A 4 nsec 4 K*1 bit two-port BiCMOS SRAM

The authors introduce a two-port BiCMOS (bipolar complementary metal-oxide semiconductor) static memory cell that combines ECL (emitter-coupled-logic)-level word-line voltage swings and emitter-follower bit line coupling with a static CMOS latch to achieve access times comparable to those of high-speed bipolar SRAMs (static random-access memories), which preserving the high density and low power of CMOS memory arrays. The memory can be accessed for read and write independently and simultaneously, making it especially attractive for the design of video, cache, and other application-specific memories. An experimental 4 K*1 bit two-port memory integrated in a 1.5- mu m-5-GHz BiCMOS technology exhibits a read access time of 4 ns and a power dissipation of 550 mW.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>