2,497 publications from this institution
Chatzinasiou, F.; Lill, C.M.; Spyrou, G.; Kypreou, K.; Stefanaki, I.; Nicolaou, V.; Evangelou, E.; Roehr, J.T.; Kodela, E.; Katsambas, A.; Tsao, H.; Ioannidis, J.P.A.; Bertram, L.; Stratigos, A.J. Author Information
This paper presents an approach to generate test vectors to characterize analog/mixed-signal circuits and its application to check the correspondence between a circuit and its HDL functional model. Interestingly, the abstract behavior of most analog circuits is a linear system, but sometimes only when viewed through a transformation of variables. When linearity holds, validation for the consistency between a circuit and a model can be efficiently performed with a small set of test vectors that grows linearly with the number of analog inputs. The linear abstraction for analog circuits also helps us distinguish different types of analog and digital I/O ports and verify their consistency effectively. We demonstrate the implemented tool by comparing a simple serial link receiver against its functional model.
The increasing speed of new generation processors will exacerbate the already large difference between CPU cycle times and main memory access times. As this difference grows, it will be increasingly difficult to build single-level caches that are both fast enough to match these fast cycle times and large enough to effectively hide the slow main memory access times. One solution to this problem is to use a multi-level cache hierarchy. This paper examines the relationship between cache organization and program execution time for multi-level caches. We show that a first-level cache dramatically reduces the number of references seen by a second-level cache, without having a large effect on the number of second-level cache misses. This reduction in the number of second-level cache hits changes the optimal design point by decreasing the importance of the cycle-time of the second-level cache relative to its size. The lower the first-level cache miss rate, the less important the second-level cycle time becomes. This change in relative importance of cycle time and miss rate makes associativity more attractive and increases the optimal cache size for second-level caches over what they would be for an equivalent single-level cache system.
SRT dividers are common in modern floating point units. Higher division performance is achieved by retiring more quotient bits in each cycle. Previous research has shown that realistic stages are limited to radix-2 and radix-4. Higher radix dividers are therefore formed by a combination of low-radix stages. In this paper, we present an analysis of the effects of radix-2 and radix-4 SRT divider architectures and circuit families on divider area and performance. Using analytical modeling and simulation, we evaluate the performance and area of a wide variety of divider architectures and implementations. We conclude that divider performance is only weakly sensitive to reasonable choices of architecture but is significantly improved by aggressive circuit techniques.
Article Vex—A CAD toolbox Share on Authors: Jules P. Bergmann Computer Systems Laboratory, Stanford University, Stanford, CA Computer Systems Laboratory, Stanford University, Stanford, CAView Profile , Mark A. Horowitz Computer Systems Laboratory, Stanford University, Stanford, CA Computer Systems Laboratory, Stanford University, Stanford, CAView Profile Authors Info & Claims DAC '99: Proceedings of the 36th annual ACM/IEEE Design Automation ConferenceJune 1999 Pages 523–528https://doi.org/10.1145/309847.309991Online:01 June 1999Publication History 3citation217DownloadsMetricsTotal Citations3Total Downloads217Last 12 Months1Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access
The Interaction Engine is a framework for prototyping interactive, connected devices based on widely available single-board Linux computers. With microcontrollers, networking, and modular open-source software, these modules enable interaction modalities such as...
Clinical trial data-sharing is seen as an imperative for research integrity and is becoming increasingly encouraged or even required by funders, journals, and other stakeholders. However, early experiences with data-sharing have been disappointing because they are not always conducted properly. Health data is indeed sensitive and not always easy to share in a responsible way. We propose 10 rules for researchers wishing to share their data. These rules cover the majority of elements to be considered in order to start the commendable process of clinical trial data-sharing: Rule 1: Abide by local legal and regulatory data protection requirements Rule 2: Anticipate the possibility of clinical trial data-sharing before obtaining funding Rule 3: Declare your intent to share data in the registration step Rule 4: Involve research participants Rule 5: Determine the method of data access Rule 6: Remember there are several other elements to share Rule 7: Do not proceed alone Rule 8: Deploy optimal data management to ensure that the data shared is useful Rule 9: Minimize risks Rule 10: Strive for excellence.
The ability to preferentially protect high-risk groups in COVID-19 is hotly debated. Here, the aim is to present simple metrics of such precision shielding of people at high risk of death after infection by SARS-CoV-2; demonstrate how they can estimated; and examine whether precision shielding was successfully achieved in the first COVID-19 wave. The shielding ratio, S, is defined as the ratio of prevalence of infection among people in a high-risk group versus among people in a low-risk group. The contrasted risk groups examined here are according to age (≥70 vs <70 years), and institutionalised (nursing home) setting. For age-related precision shielding, data were used from large seroprevalence studies with separate prevalence data for elderly versus non-elderly and with at least 1000 assessed people≥70 years old. For setting-related precision shielding, data were analysed from 10 countries where information was available on numbers of nursing home residents, proportion of nursing home residents among COVID-19 deaths and overall population infection fatality rate (IFR). Across 17 seroprevalence studies, the shielding ratio S for elderly versus non-elderly varied between 0.4 (substantial shielding) and 1.6 (substantial inverse protection, that is, low-risk people being protected more than high-risk people). Five studies in the USA all yielded S=0.4–0.8, consistent with some shielding being achieved, while two studies in China yielded S=1.5–1.6, consistent with inverse protection. Assuming 25% IFR among nursing home residents, S values for nursing home residents ranged from 0.07 to 3.1. The best shielding was seen in South Korea (S=0.07) and modest shielding was achieved in Israel, Slovenia, Germany and Denmark. No shielding was achieved in Hungary and Sweden. In Belgium (S=1.9), the UK (S=2.2) and Spain (S=3.1), nursing home residents were far more frequently infected than the rest of the population. In conclusion, the experience from the first wave of COVID-19 suggests that different locations and settings varied markedly in the extent to which they protected high-risk groups. Both effective precision shielding and detrimental inverse protection can happen in real-life circumstances. COVID-19 interventions should seek to achieve maximal precision shielding.
The covariates included within the multivariable models fitted by each paper. This is a data microarray in which the studies run along the Y-axis and the covariates run along the X-axis. Rows and columns are ordered in descending order, based on the total number each covariate was included in the multivariable models fitted by each study. Where patterns were similar between studies or covariates, those studies or covariates were placed next to each other. (PDF 82 kb)
Metagenomics deal with analysis of genetic material from environmental samples. The ultimate goal is to reconstruct entire genomes of unknown microbial species. We present a sample preparation method using the Fluidigm© C1 microfluidic platform that integrates throughput of shotgun sequencing with bioinformatics simplicity of single cell microfluidics. Our method is tested with a benchmark sample and characterize its mapping quality and coverage uniformity. We conclude that our microfluidic based pipeline is suitable for metagenomic applications.
Non-replication and inconsistency had been common features in the search for common variants of candidate genes affecting the risk of complex diseases. They may continue to require attention in the current era, when massive hypothesis-free testing of genetic variants is feasible. An empirical evaluation of the early experience with genome-wide association (GWA) studies suggests several examples where proposed associations have failed to be replicated by subsequent investigations. Non-replication and inconsistency is defined here in the framework of cumulative meta-analysis. Ideally, associations exist, GWA finds them, and subsequent investigations should replicate them. However, a number of other possibilities need to be considered. No common genetic variants may associate with the phenotype of interest and GWA may find nothing; or associations may exist, but GWA may miss them. Associations that do not exist may be falsely selected by the GWA and subsequent studies may appropriately refute them or falsely replicate them. Finally, GWA may find true associations that are nevertheless falsely non-replicated in the subsequent studies; or associations may be genuinely inconsistent across study populations. A list of options is presented for consideration in each of these scenarios.
An optical interconnect transceiver incorporates a 4-tap FIR TX to reduce VCSEL average current and an integrating/double-sampling RX to eliminate the need for a bit-rate TIA. A dual-loop CDR with baud-rate phase detection further reduces power and area. Fabricated in a 1V 90nm CMOS process, the transceiver achieves 16Gb/s operation while consuming 129mW and occupying 0.105mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>
