A 220pJ/pixel/frame CMOS image sensor with partial settling readout architecture

To reduce power consumption in a CMOS imager readout path, we use partial settling of the column values into a SAR-ADC, creating a 320H×240V prototype sensor with two column-shared 10-bit ADCs, which consumes 2.2mW at 130 fps. The measured INL and DNL with a third order correction of partial settling behavior is +1.855LSB/−1.855LSB and +0.337LSB/−0.179LSB, respectively. The input referred readout noise is 5e <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−</sup> with a conversion gain of 90uV/e <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−</sup> .