We are designing a 1mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> resolution PET (Positron Emission Tomography) system with over twenty-thousand readout channels. Multiplexing of the PSAPD (position sensitive avalanche photodiode) detectors would simplify the readout electronics and reduce the density of the circuit board design. We used simulations and experiments to study the performance of three front-end circuit configurations, 1) no multiplexing, 2) multiplexing with single-ended preamplifiers, and 3) multiplexing with differential preamplifiers, by evaluating their energy resolution and crystal identification ability. With single-ended multiplexing, there is no degradation in energy resolution but there is some degradation in crystal identification. With the novel differential multiplexing scheme presented in this paper, in simulation, there is less than 0.1dB degradation in energy resolution and no significant degradation in crystal identification. We also present a pseudo-differential technique which can be used when differential preamplifiers are not available, which we found gives a slight improvement over single-ended multiplexing.
Abstract In‐house editorials and journalistic pieces are massively published in peer‐reviewed scientific journals. This corpus has remained outside the efforts of evidence‐based medicine and research reform, and it can be imbued with unchecked biases. High‐impact journals publish such pieces massively and may generate strong support for specific narratives and perspectives. Pieces with a political slant are also a major issue. Besides high‐impact journals, across the entire scientific corpus, such pieces may be (mis)used to boost impact factors, create implausibly prolific CVs (occasionally even fraudulent) and can be powerful instruments of opinion making favouring some sponsors. Here we propose how this influential literature corpus may be strengthened to maximize its benefits and diminish its potential harms. Helpful measures to consider may include bolstering transparency (on authorship, financial compensation, disclosures of publication‐specific and generic conflicts of interest, handling of political issues, peer‐review, commissioning and timing); self‐regulation with limits per author, improvement of subject matter expertise (with experts, meta‐researchers and methodologists); balance of perspectives (with debates and for choice of topics); and post‐publication review, audit, correction and potential retraction, as needed. A systematic research agenda is needed to study better this phenomenon and also the effectiveness of proposed interventions.
Over 40 years ago, Gordon Moore wrote a short paper that has come to define this industry. In addition to the prediction that IC device counts would grow exponentially, this paper also described three main challenges to scaling: power, design cost, and what to do with the available functionality. While we have found good uses for the added functionality, power and design cost remain critical issues today, and with the ending of Dennard scaling, power looms as the largest challenge in our ability to continue to scale computing performance. This talk looks briefly at the origins of this power crisis, and then explores architectural and circuit approaches to produce energy efficient designs. The results have some interesting implications for device design.
This paper investigates the limitations on designing a processor which can sustain an execution rate of greater than one instruction per cycle on highly-optimized, non-scientific applications. We have used trace-driven simulations to determine that these applications contain enough instruction independence to sustain an instruction rate of about two instructions per cycle. In a straightforward implementation, cost considerations argue strongly against decoding more than two instructions in one cycle. Given this constraint, the efficiency in instruction fetching rather than the complexity of the execution hardware limits the concurrency attainable at the instruction level.
In this paper we explore the relationship between adder topology and energy efficiency. We compare the energy-delay tradeoff curves of selected 32- bit adder topologies, to determine how architectural features and design techniques affect energy efficiency. Optimizing different adders for the supply and threshold voltages, and transistor sizing, we show that topologies with the least number of logic stages having an average fanin of two per stage, and fewest wires are most energy efficient. While a design with fully custom sizes can be extremely tedious to layout, we show that custom sizing can be used as a guide to group different gates in the design, resulting in a manageable layout overhead without significant loss of energy efficiency.
We update prior wire scaling studies with data from the 2001 and 2002 ITRS roadmaps, extending out to the 13 nm node. Combining this data with more sophisticated wire models, over nine generations we see both local and global wires degrading relative to gates, by one and three orders of magnitude respectively. However, using repeaters for global wires as well as for the relatively few long local wires improves them significantly and makes local wires track gate delays. Inductive effects for delay are negligible, and inductive noise, given relatively lowcost design heuristics, is insignificant compared to capacitive noise. Wire aspect ratio sets capacitive coupling, and is limited to 2.2 in the ITRS roadmap to limit this noise. However, at this ratio designers already need to employ a number of noise countermeasures, whose effectiveness imply that noise need no longer be a principal reason to limit wire aspect ratios.