Managing wire scaling: a circuit perspective

We update prior wire scaling studies with data from the 2001 and 2002 ITRS roadmaps, extending out to the 13 nm node. Combining this data with more sophisticated wire models, over nine generations we see both local and global wires degrading relative to gates, by one and three orders of magnitude respectively. However, using repeaters for global wires as well as for the relatively few long local wires improves them significantly and makes local wires track gate delays. Inductive effects for delay are negligible, and inductive noise, given relatively lowcost design heuristics, is insignificant compared to capacitive noise. Wire aspect ratio sets capacitive coupling, and is limited to 2.2 in the ITRS roadmap to limit this noise. However, at this ratio designers already need to employ a number of noise countermeasures, whose effectiveness imply that noise need no longer be a principal reason to limit wire aspect ratios.