The influence of phase-locked loop on the stability of single-phase grid-connected inverter

A controlled power inverter can cause instability at its point of common coupling (PCC) with its input filter and the grid. Small-signal stability of such systems can be determined by applying the impedance-based stability criterion. The influence of the Phase-Locked Loop (PLL) on the output admittance of single-phase current-controlled inverters with different grid stiffness is analyzed in this paper. It shows that the PLL introduces a negative paralleled admittance into the output admittance of the inverter, which may lead to unintentional low-order harmonic oscillation in a weak grid. Moreover, the Second Order Generalized Integrator PLL (SOGI-PLL) and the inverse Park transformation PLL (Park-PLL) are also modeled. It is found that the quadrature signal generators of SOGI-PLL and Park-PLL play a stabilizing role in grid-inverter interactions, which thus provide promising candidates for avoiding the PLL induced instability in single-phase inverters. At last the relationship between PLL bandwidth and the Short Circuit Ratio (SCR) of the grid has been derived to guide the design of the PLL. Experimental results are presented in order to verify this analysis, and the resonant frequencies can be predicted by the method. The possible instability due to different PLL bandwidth is also demonstrated.