Techniques to reduce power in fast wide memories [CMOS SRAMs]

Bharadwaj Amrutur; Mark Horowitz

doi:10.1109/lpe.1994.573217

Abstract

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Memories contain large arrays with high capacitance bitlines and IO lines. To reduce the power of memory accesses we limit the swings on these by controlling the time the lines are driven by using a replica feedback. The swings are set to 10% of the supply over a wide range of process and operating conditions.

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