This paper describes an extractor designed to produce resistance values for use in digital circuit simulation. REDS avoids resistance extraction on most nets in a design using a simple filter based on the perimeter and area values calculated by the capacitance extractor, allowing it to concentrate on areas where resistance may substantially affect circuit timing. Nets are extracted using a fast square counting algorithm, and simplified before output to remove spurious elements. REDS is designed to work on the Magic layout database.
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