Packaging Solutions for Mitigating IGBT Short-Circuit Instabilities

In this paper, the gate voltage oscillations occurring under short-circuit conditions in Insulated-Gate Bipolar Transistors are investigated, together with their dependency with respect to stray inductance variations. By using AnSYS Q3D Extractor, electromagnetic simulations are conducted to extract the self and mutual inductances of three different layouts, which are also experimentally tested. Finiteelement device simulations on a planar IGBT cell have been carried out to provide a better understanding of the internal physical mechanisms and thus demonstrate by a sensitivity analysis which layout parameters must be minimized. This study is important to reach conclusions on the package design requirements for optimum performance under short-circuit operations, revealing the compromises between switching speed and short-circuit performance. Finally, an optimized layout solution for mitigating possible IGBT short-circuit instabilities, such as oscillations, is proposed.