In: Programming CPU/FPGA Systems from Halide (Synthesis lectures on computer architecture)
Chapter In A Book 2018 English
Authors
SB
Steven Bell
PJ
Pu Jing
JH
James Hegarty
Abstract
1 min read
In the previous chapter, we showed how the Darkroom DSL is designed from scratch to map high-level image processing algorithms to hardware. By restricting the language to stencil computations connected with line buffers, the Darkroom compiler is able to lower designs to hardware and software, with no implementation detail provided by the programmer.
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