Low-Thermal-Budget Excimer-Laser Crystallization of Hf _0.5 Zr _0.5 O ₂ with UV-Transparent Dielectric Capping: A Unified Platform for BEOL and Oxide-TFT Backplanes

Low-temperature integration of ferroelectrics remains a bottleneck for semiconductor back-end-of-line (BEOL) and display backplane devices, where temperature-sensitive interconnects and substrates strictly limit thermal budgets. We present a unified, low-thermal-budget platform that crystallizes ALD-grown Hf 0.5 Zr 0.5 O 2 (HZO) into a robust ferroelectric by combining a deep-UV-transparent dielectric capping layer with excimer laser annealing (ELA, 248 nm). This flow enables local phase transformation with minimal thermal budget and is compatible with large-area and flexible form factors. Amorphous HZO was deposited by thermal ALD using alternating HfO 2 /ZrO 2 cycles in a 1:1 ratio to realize Hf:Zr=1:1 stoichiometry. A conformal wide-bandgap dielectric cap was subsequently grown by ALD. During ELA, the cap provides high transmission at 248 nm to deliver optical energy into HZO and helps maintain surface/interface integrity under nanosecond thermal excursions. In pulsed-laser processing of thin films, transient melting can lead to instabilities such as ablation; capping layers are widely used to mitigate such risks. By optimizing fluence–pulse conditions, we locally crystallize HZO into the orthorhombic ferroelectric phase without elevating the global substrate temperature, preserving BEOL compatibility and accommodating polymer/glass stacks common in display processing. Our analysis and initial results indicate that the cap thickness co-influences mechanical confinement and cooling behavior under nanosecond heating: insufficient thickness can limit surface protection and orthorhombic stabilization, whereas excessive thickness may increase constraint and narrow the usable process window. Within a practically identified working range, the method yields large remanent polarization (high 2P r ), low coercive voltage, reduced leakage, and excellent reliability. Representative ferroelectric transistors on oxide semiconductors exhibit wide memory windows, low-voltage operation, strong retention, and endurance exceeding 10 9 switching cycles. A practical process map (fluence–pulse–cap thickness) is outlined to reproducibly achieve these metrics while suppressing wake-up and device-to-device variability. The same processing concept translates across platforms. For embedded FeFET arrays in BEOL, the approach minimizes thermal cross-talk to underlying metals and dielectrics and supports non-volatile operation at low voltage. For oxide-TFT display backplanes, ELA-assisted crystallization is compatible with temperature-sensitive channel/passivation stacks, supporting low-power pixel control and enabling opportunities for compute-in/near-pixel functions without exceeding substrate limits. Capping-layer selection is guided by two manufacturability constraints: (a) sufficient transmission at the laser wavelength and (b) selective removability versus crystalline HZO after crystallization. These criteria can be satisfied by ALD-accessible wide-bandgap oxides with appropriate wet-etch contrast. Further implementation details are beyond the scope of this abstract and will be presented. Keywords: ferroelectric HZO, atomic layer deposition, excimer laser annealing, UV-transparent dielectric capping, BEOL compatibility, oxide-TFT backplanes, low-thermal-budget processing, FeFET