Double-Gate Igzo-Based Fefet with ZrO₂ Seed Layer and HfO₂/ZrO₂ Superlattice for Low-Temperature Ferroelectric Phase Stabilization

Hafnium–zirconium oxide (HfₓZr₁₋ₓO₂, HZO)-based ferroelectric field-effect transistors (FeFETs) have emerged as promising candidates for next-generation logic-in-memory and neuromorphic computing systems, owing to their nonvolatile memory capability, high integration density, and CMOS compatibility. Their fast, low-power operation with in-memory computing capability makes them highly attractive for AI hardware accelerators. However, integrating oxide semiconductor channels such as indium gallium zinc oxide (IGZO) into ferroelectric transistor stacks remains challenging due to the thermal sensitivity of the channel. Exposure to a high thermal budget during fabrication can degrade carrier transport, induce threshold voltage instability, and generate donor-like defects associated with oxygen vacancies. Achieving stable ferroelectric switching below 400 °C is thus critical for enabling back-end-of-line (BEOL) integration while preserving channel performance and reliability. In this work, we propose a double-gate FeFET structure designed to realize low-temperature ferroelectric switching while preserving IGZO channel properties. The key elements are (i) a ~2 nm zirconium oxide (ZrO₂) seed layer directly interfaced with the IGZO channel and (ii) a ~0.5–0.6 nm periodic hafnium oxide/zirconium oxide (HfO₂/ZrO₂) superlattice (SL) gate insulator, both formed via thermal-assisted atomic layer deposition (THALD). This interface and phase-engineered stack stabilizes the orthorhombic ferroelectric phase at low temperature, eliminating the need for conventional high-temperature (>450 °C) crystallization. The SL design also suppresses the formation of the monoclinic phase, which is detrimental to polarization switching. The IGZO channel, ~7 nm thick, was deposited by RF sputtering under high oxygen partial pressure to suppress intrinsic donor-like defects and ensure high resistance in the off-state. Subsequent dry-air annealing and mild oxygen plasma treatment were applied to improve the channel’s insulating properties and passivate the IGZO/HZO interface. This process integration minimized charge trapping, reduced interface state density, and enabled a ferroelectric switching interface that remains stable under low thermal budget conditions. Electrical characterization showed a clear counterclockwise hysteresis curve with a memory window of ~1.5 V under ±3 V program/erase conditions, demonstrating low-voltage and stable ferroelectric operation. The device maintained stable endurance over multiple program/erase cycles and exhibited robust retention characteristics without significant threshold voltage degradation. Initially, a slight “weak erase” asymmetry was observed but was recovered after a short wake-up cycle, indicating stabilization of interface defect states and uniform polarization switching across the gate insulator. The double-gate structure further improved electrostatic control, contributing to enhanced subthreshold swing (SS) and reduced short-channel effects. These results demonstrate the feasibility of achieving low-temperature ferroelectric switching through interface and phase engineering. The combination of a ZrO₂ seed layer and nanoscale HfO₂/ZrO₂ superlattice enables orthorhombic phase stabilization below 400 °C while preserving the electrical stability of the thermally sensitive IGZO channel. This approach opens new possibilities for fabricating high-density, low-power nonvolatile memory and computing devices with BEOL compatibility, paving the way for next-generation system-on-chip (SoC) integration and AI hardware applications. Keywords: ferroelectric field-effect transistor, IGZO, HZO, ZrO₂ seed layer, superlattice, low-temperature crystallization, oxide semiconductor, interface engineering Figure 1