High Speed Matrix Multiplication Implementation Using Field Programmable Gate Array

operations are commonly used in almost all areas of scientific research. Matrix multiplication has significant application in the areas of graph theory, numerical algorithms, signal processing, and digital control. Matrix multiplication is a computationally intensive problem, especially the design and efficient implementation on an FPGA where resources are very limited, has been more demanding. In this paper, we implement an architecture that is capable of handling matrices of variable sizes. This design minimize the gate count, area, improvements in latency, computational time, throughput for performing matrix multiplication and reduce the number of multiplication and additions hardware required to get the matrices multiplied on commercially available FPGA devices. The hardware design in our work to multiply two numbers is use the multiplier unit used for multiplying two numbers in a single clock cycle. This increases the speed of the computation. The system is simple to implement and is highly scalable, the system can be scaled with simple repetition of the hardware and with no changes in the algorithm. Our approach converts matrix multiplication in programmable processors into a computation channel, when increasing the processing throughput, the output noise (error) increases due to computational errors caused by exceeding the machine-precision limitations.