Array-of-arrays architecture for parallel floating point multiplication

This paper presents a new architecture style for the design of a parallel floating point multiplier. The proposed architecture is a synergy of trees and arrays. Architectural models were designed to implement the 53-bit mantissa path of the IEEE standard 754 for floating point multiplication, and tested for functionality in Verilog. The design, which was done in dual-rail domino, simulated in HSpice with estimated capacitive load models in a 1 /spl mu/m CMOS technology. Multiplication latency of 10 ns (23.3 FO4) at 4.3 V supply and 120/spl deg/C can be achieved with the best topology of the array-of-arrays architecture. The estimated multiplier area is 3 mm/spl times/6 mm.