Electrical parasitics and thermal modeling for optimized layout design of high power SiC modules

The reliability of power modules is closely depended on their electrical and thermal behavior in operation. As power modules are built to operate more integrated and faster, the electrical parasitic and thermal stress issues become more critical. This paper investigates simplified thermal and parasitic inductance models of SiC power modules. These models can replace the models by Finite Element Methods (FEM) to predict temperatures and electrical parasitics of power modules with much faster speed and acceptable errors and will be used for study of real operation of power modules. As a case study, the presented models are verified by a conventional and an optimized power module layout. The optimized layout is designed based on the reduction of stray inductance and temperature in a P-cell and N-cell half-bridge module. The presented models are verified by FEM simulations and also experiment.