Efficient on-chip global interconnects

We present circuits for a high-efficiency low-swing interconnect scheme suitable for the Smart Memories reconfigurable architecture. By using a separate supply, global clocking, and differential signaling, we reduce design complexity; and by using overdrive circuits, equalization techniques, and sense-amplifiers we retain high performance. A testchip built in a 1.8 V 0.18-/spl mu/m technology consumed <1pJ/bit for a 10 mm bus at 1 GHz, a power savings over full-swing signaling of up to 10 x, and demonstrated amplifier input offset voltages of under 100 mV.