Architecture and circuit techniques for a reconfigurable memory block

A 2 kB reconfigurable SRAM block, using self-timed, pulse-mode circuits capable of emulating a portion of a cache or a streaming FIFO is realized in a 1.8 V 0.18 /spl mu/m CMOS process and operates at 1.1 GHz (10F04 cycle). The additional logic needed for reconfigurability consumes 26% of the total power and 32% of the total area.