A semi-digital DLL with unlimited phase shift capability and 0.08-400 MHz operating range

The DLL consists of two loops. The core loop is a first order DLL generating six edges evenly spaced by 30/spl deg/. The peripheral digital loop selects a pair of edges, /spl phi/ and /spl psi/, to interpolate. To cover the 360/spl deg/ desired range, the edges can be selectively inverted. The resulting edges, /spl phi/' and /spl psi/', drive a digitally-controlled interpolator that generates the main clock /spl Theta/. The interpolator quantization step is 2/spl deg/, i.e. 22ps for a 250MHz clock. This dual-loop architecture provides unlimited phase shift capability eliminating start-up issues and phase relationship constraints. The only requirement is that the DLL input clock and the reference clock are plesiochronous making this architecture suitable for clock-recovery applications.