A portable digital DLL architecture for CMOS interface circuits
Article 2002 English
Authors
BG
B.W. Garlepp
KD
Kevin Donnelly
JK
Jun Kim
Abstract
1 min read
A digital DLL was developed which achieves infinite phase range and 40 ps worst-case phase resolution at 400 MHz. The architecture uses dual delay lines with an end-of-cycle detector, phase blenders, and duty cycle correctors. This more easily process-portable DLL achieves jitter performance comparable to a more complex analog DLL, when placed into identical high-speed interface circuits fabricated on the same die in a 0.4 /spl mu/m CMOS process.
B.W. Garlepp, Kevin Donnelly, Jun Kim, P.S. Chau, Jared Zerbe, Ching-Chao Huang, Chanh Tran, C.L. Portmann, D. Stark, Yiu-Fai Chan, T.H. Lee, Mark Horowitz
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