This paper describes the design of a high speed interface for a multiprocessor interconnection network. To achieve higher transfer rates, the interface utilizes a voltage swing of 1 V, a Delay Line PLL and sampling of the data on both edges of the clock. Chips fabricated in a 0.8 pm CMOS technology achieve transfer rates of 700 Mbpdpin operating from a 3.3-V supply. Worst case measured peak-to-peak clock jitter is 260 ps (63 ps RMS). The layout area occupied by the DLL and the associated clock duty cycle adjuster is 460x800 pni2.
B.W. Garlepp, Kevin Donnelly, Jun Kim, P.S. Chau, Jared Zerbe, Ching-Chao Huang, Chanh Tran, C.L. Portmann, D. Stark, Yiu-Fai Chan, T.H. Lee, Mark Horowitz
B.W. Garlepp, Kevin Donnelly, Jun Kim, P.S. Chau, Jared Zerbe, Ching-Chao Huang, Chanh Tran, C.L. Portmann, D. Stark, Yiu-Fai Chan, T.H. Lee, Mark Horowitz
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