A dependency graph based methodology for parallelizing HLL applications on FPGA (abstract only)

Reconfigurable computing is an exciting new area of research. It opens up a number of new computing paradigms with the potential to significantly change the embedded computing landscape. Unfortunately, as with any new concept, there is much to be done before it can be brought into the mainstream. Reconfigurable computing needs to be made more usable by the general computing community by making the application mapping process more user transparent. We need to be able to efficiently exploit the parallelism and high communications bandwidth available in reconfigurable computing systems, such as provided by FPGA devices. In this paper we propose a framework to map C-based applications to an FPGA based system. The framework relies on dependency based analysis information obtained from a high level Intermediate Representation (IR) of the C-Application. The dependencies have a major impact on the instruction flow and the parallelism of the algorithms when implemented on FPGA based high performance computing platforms. We demonstrate the importance of these dependencies in algorithms by examining a compute intensive bio-informatics application. Targeting on a Xilinx Virtex 5 XC5VFX70T FPGA, our place and route results achieved 92% of the clock frequency achieved by using a manual design of the same application. The contribution in this paper is to provide a semi-automated approach to generate hardware for FPGA based systems through a high level data dependency graphical IR.