An FPGA model for developing dynamic circuit computing

Computing on SRAM based FPGAs is set to challenge the instruction set architecture (ISA) computing paradigm in the high-performance computing arena. Dynamic circuit computing (DCC) techniques increase flexibility and make more efficient use of an FPGA. However, the rapid prototyping heritage of the FPGA has resulted in software that is inadequate for exploiting this potential to be a flexible computing platform. A major barrier to the increased use of high performance computing on FPGA is the high computational overhead associated with the management of a DCC system. The ability to explore new approaches in compiler and execution environment design is crucial in order to reduce these overheads. In this paper we report on the development of an open FPGA architecture model and open source compiler tools for the exploration of the complex interaction between the architecture, compiler and execution environment for DCC on FPGA.