In this Viewpoint, Ioannidis and coauthors compare overuse of computed tomography and magnetic resonance image scanning with large-scale haphazard population screening for disease and call for dedicated investigations to understand how to reduce unnecessary and wasteful diagnostic imaging.
A completion-detection method is proposed for efficiently implementing Boolean functions as self-timed logic structures. Current-sensing completion detection (CSCD) allows self-timed circuits to be designed using single-rail variable encoding (one signal wire per logic variable) and implemented in about the same silicon area as an equivalent synchronous implementation. Compared to dual-rail encoding methods, CSCD can reduce the number of signal wires and transistors used by approximately 50%. CSCD implementations improved performance over equivalent dual-rail designs because of: reduced parasitic capacitance, removal of spacer tokens in the data stream, and computation state similarity of consecutive data variables. Several CSCD configurations are described and evaluated and transistor-level implementations are provided for comparison.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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Maintaining low supply impedance is a critical task in modern high-performance chip and system design, and this depends on how the current flows on the chip, package, and board power distribution layers. Using a simple inductive pickup loop previously described, we measure the per-pin via currents for a large VLSI chip in operation. Interestingly, the variation in AC current across the package was only 33%, indicating that for this chip current crowding was not an issue. Furthermore, we measured the board bypass capacitance currents as well, and found that the capacitors supplied between 80% and 120% of the peak transient currents of the pins to which they were connected. Since the maximum current is only slightly larger than the current required by the attached pin, the board bypass capacitance primarily affects the pin it is connected to, and does not really bypass the other VDD pins in that region.
Despite their use in analog or mixed-signal applications, the high power overheads of traditional linear regulators (both series and shunt) have precluded their successful adoption in regulating the supply of energy-efficient digital circuits. In this paper, we show that linear regulation can in fact reduce the effective supply impedance of digital circuits without increasing their total power dissipation. Achieving this goal requires minimizing the static power dissipation of the regulator, leading to a push-pull topology (similar to the regulators demonstrated by Wu and Sanders, 2001, Poon et al, 1999, and Intersil, 1998) with comparator-based feedback and a switched source-follower output stage. Measured results from a regulator implemented in a 65 nm SOI test-chip verify that by using these techniques, regulation reduces the effective supply noise by ~30% while also enabling a slight decrease (1.4%) in total power dissipation.
Energy-efficient computation is critical if we are going to continue to scale performance in power-limited systems. For floating-point applications that have large amounts of data parallelism, one should optimize the throughput/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> given a power density constraint. We present a method for creating a trade-off curve that can be used to estimate the maximum floating-point performance given a set of area and power constraints. Looking at FP multiply-add units and ignoring register and memory overheads, we find that in a 90 nm CMOS technology at 1 W/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , one can achieve a performance of 27 GFlops/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> single precision, and 7.5 GFlops/mm double precision. Adding register file overheads reduces the throughput by less than 50 percent if the compute intensity is high. Since the energy of the basic gates is no longer scaling rapidly, to maintain constant power density with scaling requires moving the overall FP architecture to a lower energy/performance point. A 1 W/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> design at 90 nm is a "high-energy" design, so scaling it to a lower energy design in 45 nm still yields a 7× performance gain, while a more balanced 0.1 W/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> design only speeds up by 3.5× when scaled to 45 nm. Performance scaling below 45 nm rapidly decreases, with a projected improvement of only ~3x for both power densities when scaling to a 22 nm technology.
This paper presents a high speed receiver design that utilizes current integration in order to increase its noise immunity. The integration of current on a capacitor based on the incoming signal voltage effectively averages the incoming signal over its valid time period, therefore filtering out high frequency noise. An experimental design illustrating the concept has been fabricated in a 1.2 /spl mu/m CMOS technology. The receiver dissipates 2.7 mW of power operating from a 5-V supply, achieves error free operation at a clock frequency of 250 MHz, and occupies 60/spl times/450 /spl mu/m/sup 2/ of silicon area.
Rsim is a switch-level simulator that can simulate large digital MOS integrated circuits up to three orders of magnitude faster than SPICE. Unfortunately, Rsim's simplified circuit models and timing analysis prevent it from simulating "difficult" CMOS circuits and circuits containing bipolar transistors. We address this shortcoming by adapting Rsim to use more general piecewise linear models. We show that these modifications can be made in a way that preserves Rsim's efficiency for the simplest cases. The result is a simulator that can approach the efficiency of dedicated switch-level simulators when switch-level models are used. Alternatively, greater accuracy and flexibility can be obtained when more sophisticated models are used.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
