2,497 publications from this institution
<p>PDF - 27KB, Percentage of CEC papers published each year that are linkage studies or GWAS.</p>
In 2019, before the covid-19 pandemic, we highlighted the unprecedented promise and peril surrounding the quantity, quality, and integrity of scientific research. 1 The pandemic has been a crash test for scientific publishing, emphasising the great successes and failures, and the promise and perils of current systems.In 2020 because of the pandemic, we announced a postponement of the ninth international congress on peer review and scientific publication.We now confirm plans to hold the meeting on 8-10 September 2022 and announce the official call for abstracts.The aim of the congress is to encourage research into the quality and credibility of peer review and scientific publication and to further the evidence base on which scientists can improve the conduct, reporting, and dissemination of scientific research.As with the previous eight congresses, 2 the ninth will feature three days of presentations of original research about processes, policies, problems, and innovations related to peer review, scientific publication, and research dissemination.Participants will include editors and publishers of scientific peer reviewed journals, researchers, funders, bibliometric and informatics experts, information innovators, librarians, journalists, policy makers, ethicists, scientific information producers and disseminators, and anyone interested in the progress of the scientific information enterprise and the quality of scientific evidence.The congress embraces a wide range of disciplines, including (but not limited to) biomedicine, health and life sciences, applied sciences, basic sciences, physical and chemical sciences,
•Challenges of rapid COVID-19 drug development risk to compromise good scientific practice•Access to patient-level data especially urgent to address risks of protocol violations and rapid reviews.•Open access to data enables transparency, secondary analyses, and meta-analyses.•Politicization of scientific reports will be reduced by cross-checking and multilateral analyses.
We describe circuit techniques for a Flash memory which operates with a V/sub DD/ of 1.5 V. For the interface between the peripheral circuits and the memory core circuits, two types of level shifter circuits are proposed which convert a V/sub DD/ level signal into the high voltage signals needed for high performance. In order to improve the read performance at a low V/sub DD/, a new self-bias bitline voltage sensing scheme is described. This circuit greatly reduces the delay's dependence on bitline capacitance and achieves 19 ns reduction of the sense delay at low voltages. Multilevel storage sensing with this circuit is also discussed.
A single-chip functional tester for VLSI circuits that integrates the vector memory, the error memory, a decompressor, and 16 sets of independently controlled pin electronics on a 9.0*9.4-mm chip is described. The device contains over 200 K transistors and is fabricated using a 1.6- mu m CMOS technology. The integrated pin electronics support a per-pin tester architecture, allowing the transitions for each pin to be independently adjusted to better than 1 ns. The chip dissipates less than 0.75 W running at 25 M vectors/s. By integrating all tester functions on a single chip, it is possible to build all extremely compact tester. A 256-pin tester requires only 16 chips. This size makes it possible to reduce the length of the transmission line between the device under test and the tester to under 10 cm, minimizing signal reflections and enabling the delivery of high-fidelity waveforms.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>